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FEATURES
* SRAM-based, in-system programmable * Switch Matrix -- Non-Blocking -- Identical and predictable delays -- One-to-one, one-to-many and many-to-one connections
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* RapidConfigureTM parallel interface for fast, incremental configuration of Switch Matrix and I/O Port attributes -- 100% JTAG compliant * Clocked, Latched and Flow-through Dataflow Modes -- As low as 7.5 ns pin-to-pin delay in flow-through mode and 133 MHz clock rate in registered mode * I/O Ports -- Individually programmable as input, output or bidirectional -- For each I/O Port, clock, clock enable, input enable and output enable can be selected independently from a large pool of common control signals -- 12 mA current drive -- Separated I/O power pins for easy interfacing between 5V and 3.3V signals
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IQX Family Data Sheet
DESCRIPTION
The IQX family of SRAM-based bit-oriented switching devices is manufactured using a 0.6 m CMOS process. These devices offer clock speeds of up to 133 MHz and pin-to-pin delay as low as 7.5 ns. The IQX devices are used in applications requiring dynamic switching and flexible routing / interconnection of signals. These applications include communication switches, network systems, DSP / image processing engines and file/video servers. At the heart of IQX devices is a non-blocking Switch Matrix. A line in the Switch Matrix can be connected to one or more other lines. The Switch Matrix lines are connected to I/O Ports with programmable functional attributes. The RapidConfigure parallel interface allows connections in the Switch Matrix to be changed quickly and incrementally. This interface can also be used to configure I/O Port attributes individually and incrementally. In either case, data integrity is maintained on all unchanged signal paths through the device. The IQX devices support the industry standard JTAG (IEEE 1149.1) interface for boundary scan testing. The same interface can also used for serially downloading the configuration bit stream into the devices.
Shared with I/O Control Signals
Shared with RapidConfigure Interface Signals
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I/O Port I/O Port I/O Port I/O Port I/O Port I/O Port I/O Port
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Dedicated I/O Control Signals
I/O Control
Signal Ports
Switch Matrix [Crossbar Array]
RapidConfigure Interface JTAG Configuration Control
TDO TDI TMS TCK TRST* Figure 1. IQX Functional Block Diagram
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IQX Family Data Sheet
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Contents
Features ........................................................................................................................................................1 Description...................................................................................................................................................1 1.0 Architecture ..........................................................................................................................................9 1.1 Non-blocking Switch Matrix ..........................................................................................................9 1.1.1 Switch Control ......................................................................................................................9 1.2 Programmable I/O Port .................................................................................................................10 1.2.1 Programmable Pull-up Current ............................................................................................10 1.2.2 Pin and Array Side Trickle Current .....................................................................................10 1.2.3 I/O Port Functional Mode ....................................................................................................10 1.3 I/O Control Signals .......................................................................................................................14 1.3.1 Clock Control.......................................................................................................................15 1.3.2 Tristate Control ....................................................................................................................15 1.3.3 Neighboring I/O Port As A Control Source.........................................................................15 1.3.4 Key Control Pins as a Control Source .................................................................................15 1.3.5 Default Values for Control Signals......................................................................................15 1.4 RapidConfigure (RC) Interface ....................................................................................................15 1.4.1 Switch Matrix Connection Changes ....................................................................................16 1.4.2 I/O Port Configuration .........................................................................................................18 1.4.3 I/O Port Configuration Holding Register.............................................................................18 1.4.4 I/O Port Configuration Register Contents ...........................................................................21 1.4.5 Reset Commands .................................................................................................................21 1.5 JTAG-based Configuration Controller .........................................................................................22 1.5.1 JTAG Interface ....................................................................................................................22 1.5.2 I/O Port Configuration .........................................................................................................22 1.5.3 Switch Matrix Configuration ...............................................................................................22 1.5.4 Mode Control Register Configuration .................................................................................22 2.1 Device Reset .................................................................................................................................23 2.2 Mixed Voltage Operation .............................................................................................................23 2.3 Power Pin VDD.X..........................................................................................................................23 2.4 Mode Control Register..................................................................................................................24 3.0 In System Configuration Using JTAG-based Configuration Controller ............................................25 3.1 Bit Stream Generation ..................................................................................................................25 3.2 Bit Stream Downloading ..............................................................................................................25 3.3 Configuring Multiple IQX Devices ..............................................................................................26 4.0 Pin Summary.......................................................................................................................................27 5.0 Electrical Specifications .....................................................................................................................29 5.1 Absolute Maximum Ratings (1) ................................................................................................29 5.2 Recommended Operating Conditions ........................................................................................29 5.3 Capacitance (3) ..........................................................................................................................29 5.4 DC Electrical Specifications .........................................................................................................30 5.5 AC Electrical Specifications for IQX320 and IQX240B..............................................................31
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Contents
5.6 AC Electrical Specifications for IQX160 and IQX128B..............................................................33 5.7 Parameter De-rating For One-to-Many Connections....................................................................35 5.8 Test Circuit and Timing Diagrams ...............................................................................................36 6.0 Pinout ..................................................................................................................................................43 6.1 IQX320 [PBGA/416L] Package Pinout by Name ........................................................................43 6.2 IQX320 [PBGA/416L] Package Pinout by Location ...................................................................44 6.3 IQX320 [PBGA/416L] Package Footprint ...................................................................................45 6.4 IQX240B [PQFP/304L] Package Pinout by Name.......................................................................46 6.5 IQX240B [PQFP/304L] Package Pinout by Location ..................................................................47 6.6 IQX240B [PQFP/304L] Package Pinout ......................................................................................48 6.7 IQX160 [PQFP/208L] Package Pinout by Name .........................................................................49 6.8 IQX160 [PQFP/208L] Package Pinout by Location ....................................................................50 6.9 IQX160 [PQFP/208L] Package Pinout.........................................................................................51 6.10 IQX128B [PQFP/184L] Package Pinout by Name.....................................................................52 6.11 IQX128B [PQFP/184L] Package Pinout by Location ................................................................53 6.12 IQX128B [PQFP/184L] Package Pinout ....................................................................................54 7.0 Mechanical Specification....................................................................................................................55 7.1 IQX320 [PBGA/416L] Package Dimensions ...............................................................................55 7.2 PQFP Package Dimensions .........................................................................................................56 8.0 Package Thermal Characteristics........................................................................................................57 9.0 Tables for Determining Die Pad to I/O Port Pin Mapping and Locations of Real SRAM Cell ....... 58 10.0 Component Availability and Ordering Information .........................................................................62 11.0 IQX Family at a Glance ....................................................................................................................63 12.0 Product Status Definitions ................................................................................................................64
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Figures
Figure 1. IQX Functional Block Diagram ..................................................................................................1 Figure 2. Switch Matrix Structure ..............................................................................................................9 Figure 3. Switch Matrix Control...............................................................................................................10 Figure 4. Programmable I/O Port .............................................................................................................10 Figure 5. IQX Output Driver and Pull-Up Current...................................................................................10 Figure 6. I/O Control ................................................................................................................................14 Figure 7. IQX RapidConfigure System Interface .....................................................................................16 Figure 8. Reset Circuit ..............................................................................................................................23 Figure 9. Off-line Bit Stream Generation .................................................................................................25 Figure 10. Embedded Bit Stream Generation ...........................................................................................25 Figure 11. Configuring Multiple IQX Devices.........................................................................................26 Figure 12. Test Circuit and Waveform Definition....................................................................................36 Figure 13. Registered Input and Registered Output Mode Timing (ICLK, OCLK Synchronized)..........36 Figure 14. Registered Input Mode Timing ...............................................................................................36 Figure 15. Registered Output Mode Timing.............................................................................................37 Figure 16. I/O Port Timing (Flow-through Mode)...................................................................................37 Figure 17. Input Enable Timing (Flow-through Mode) ...........................................................................37 Figure 18. Output Enable Timing (Flow-through Mode) ........................................................................38 Figure 19. Latched Input Mode Timing....................................................................................................38 Figure 20. Latched Output Mode Timing .................................................................................................38 Figure 21. Key Timing for Register Input, Clock Enable (CKE).............................................................39 Figure 22. Key Timing for Register Output, Clock Enable (CKE) ..........................................................39 Figure 23. Key Timing for Input Enable ..................................................................................................39 Figure 24. Key Timing for Output Enable................................................................................................40 Figure 25. Key Timing for Latch Input, Enable (CKE)............................................................................40 Figure 26. Key Timing for Latch Output, Enable (CKE) .........................................................................40 Figure 27. Key Counter Timing................................................................................................................41 Figure 28. RapidConfigure Timing ..........................................................................................................41 Figure 29. JTAG Timing ..........................................................................................................................42 Figure 30. IQX320 [PBGA/416L] Package Footprint..............................................................................45 Figure 31. IQX240B [PQFP/304L] Package Pinout ..................................................................................48 Figure 32. IQX160 [PQFP/208L] Package Pinout ...................................................................................51 Figure 33. IQX128B [PQFP/184L] Package Pinout.................................................................................54 Figure 34. IQX320 [PBGA/416L] Package Dimensions..........................................................................55 Figure 35. PQFP Package Dimensions .....................................................................................................56
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Tables
Table 1. Summary of Programmable I/O Attributes for IQX Devices .....................................................11 Table 2. RapidConfigure Interface Pin Count ..........................................................................................16 Table 3. RapidConfigure Options .............................................................................................................16 Table 4. Changing Switch Matrix Connections Using RapidConfigure ..................................................17 Table 5. Configuring I/O Ports Using RapidConfigure Interface.............................................................18 Table 6. I/O Port Configuration Bits ........................................................................................................19 Table 7. I/O Configuration Register Contents ..........................................................................................21 Table 8. RapidConfigure Reset Commands .............................................................................................22 Table 9. Device Reset ...............................................................................................................................23 Table 10. Mode Control Register Bit Assignment ...................................................................................24 Table 11. Number of JTAG Cycles and Configuration Time (using a 10 MHz JTAG Clock) ................26 Table 12. IQX Pin Summary ...................................................................................................................27 Table 13. Supply Voltage Source .............................................................................................................28 Table 14. Absolute Maximum Ratings .....................................................................................................29 Table 15. Recommended Operating Conditions.......................................................................................29 Table 16. Capacitance...............................................................................................................................29 Table 17. DC Electrical Specifications.....................................................................................................30 Table 18. AC Electrical Specifications for IQX320 and IQX240B..........................................................31 Table 19. AC Electrical Specifications for IQX160 and IQX128B..........................................................33 Table 20. Parameter De-rating For One-to-Many Connections................................................................35 Table 21. IQX320 [PBGA/416L] Package Pinout by Name ....................................................................43 Table 22. IQX320 [PBGA/416L] Package Pinout by Location ...............................................................44 Table 23. IQX240B [PQFP/304L] Package Pinout by Name ..................................................................46 Table 24. IQX240B [PQFP/304L] Package Pinout by Location..............................................................47 Table 25. IQX160 [PQFP/208L] Package Pinout by Name .....................................................................49 Table 26. IQX160 [PQFP/208L] Package Pinout by Location ................................................................50 Table 27. IQX128B [PQFP/184L] Package Pinout by Name ..................................................................52 Table 28. IQX128B [PQFP/184L] Package Pinout by Location..............................................................53 Table 29. PQFP Package Dimensions ......................................................................................................56 Table 30. Package Thermal Coefficients ..................................................................................................57 Table 31. IQX320 and IQX240B I/O Port Pin Mapping ..........................................................................59 Table 32. IQX160 and IQX128B I/O Port Pin Mapping ..........................................................................61 Table 33. Component Availability............................................................................................................62 Table 34. Ordering Information................................................................................................................62 Table 35. IQX Family at a Glance ............................................................................................................63
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IQX Family Data Sheet 1.0 ARCHITECTURE
IQX devices are SRAM-based bit-oriented switching matrices. The devices can be configured and controlled in-system by storing appropriate data into the internal SRAM cells and configuration registers. As shown in Figure 1, the main functional blocks of the device are the non-blocking Switch Matrix, Programmable I/O Ports, I/O Control signal block, RapidConfigure Configuration Interface and a JTAG-based Configuration Controller. The full-featured programmable I/O Ports are connected to the corresponding lines in the Switch Matrix. The I/O Port control signals such as clock, clock enable, input enable, and output enable are used to control the flow of data through the I/O Ports. The JTAG-based configuration controller is used to download the configuration bit stream serially into the I/O Port configuration registers and Switch Matrix SRAM cells, thereby establishing the desired functional attributes for the I/O Ports and connections among them through the Switch Matrix. Alternatively, the RapidConfigure parallel interface may be used to load the configuration data in the I/O Port Configuration Registers and Switch Matrix SRAM cells. The use of RapidConfigure interface enables quick configuration changes.
Pass Transistors SRAM Cells Permanent Connections Signal Lines
0
Programmable I/O Buffers 12 34567
I/O Port Pins Figure 2. Switch Matrix Structure
1.1 Non-blocking Switch Matrix
The Switch Matrix is an x-y routing structure (or grid). Each horizontal signal trace is hardwired to a corresponding vertical signal trace as shown by the junction dots in Figure 2. An I/O Port pin connects to this horizontal-vertical trace pair through a programmable buffer. Signal paths through the Switch Matrix are very well balanced, resulting in predictable and uniform pin-topin delays. A pass transistor whose ON/OFF state is controlled by a dedicated SRAM cell is placed at the intersection of two different signal lines. Signal multicasting/broadcasting operation is supported by allowing a Switch Matrix line carrying an incoming signal to be connected to multiple Switch Matrix lines carrying outgoing signals. Signal multiplexing is supported by allowing multiple Switch Matrix lines carrying incoming signals (controlled using input enable signals) to be connected to the same Switch Matrix line carrying an outgoing signal. It is also possible to create a common internal node among multiple Switch Matrix lines by making all pair-wise connections among these signal lines, and driving such a node by configuring the corresponding I/O Ports in the Bus Repeater mode. Refer to the section on "I/O Port Functional Mode" for more details.
1.1.1 Switch Control As shown in Figure 3, there are two possible switch and SRAM cell locations for a connection between any two Switch Matrix lines. For example, the two possible switch (and SRAM cell) locations controlling a connection between signal lines i and j are row i (word i) and column j (bit j), or row j and column i. Only one location is populated with a switch and the controlling SRAM cell. This location is called the real location while the other one is referred to as the ghost location. The real cell locations form a unique pattern on the device die as described in Appendix A. The section on "RapidConfigure Interface" explains how this knowledge can be used to reduce the time it takes to change Switch Matrix connections.
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IQX Family Data Sheet
1.2.1 Programmable Pull-up Current
CA0 CA1 Column (bit) Address CAm-1
Column (bit) Address Decoder
As shown in Figure 5, the I/O Port contains several n-channel pull-up devices. The normal pull-up current is supplied by a device which is switched on/off by internally generated control signal. An additional static pull-up current (IPU-WK) or (IPU-SG) can be programmed at each I/O Port pin. This additional pull-up current is primarily used for but not restricted to the Bus Repeater (BR) mode.
VDD.PAD PU B C D I/O Port
RA1
Row (word) Address Decoder
RA0
(j, i) I/O Port Buffers Pj
Row (word) Address
(i, j)
RAm-1
I/O Port Buffers
Pi
PD
A
Figure 3. Switch Matrix Control
A)Pull Down B)Normal Pull Up C)Additional Weak Pullup D)Additional Strong Pullup
1.2 Programmable I/O Port
Each signal line in the Switch Matrix is connected to a programmable I/O Port. The functional attributes of individual I/O Ports can be programmed independently. The I/O Port attributes include its signal direction (in, out or bidirectional), data flow mode (flow-through, registered or latched), and pull-up current. Figure 4 shows the structure of the programmable I/O Port. The sources for the four control signals: clock (CLK), clock enable (CKE), input enable (IE), and output enable (OE) are also programmable and are described later in the section "I/O Control Signals."
Figure 5. IQX Output Driver and Pull-Up Current
1.2.2 Pin and Array Side Trickle Current N-channel devices are used as a trickle current source (nominally 10 A) on the pin side and array side for each I/O Port. Upon reset, these current sources are turned ON. They can be turned OFF by configuring the I/O Port. 1.2.3 I/O Port Functional Mode Table 1 describes the various modes of the I/O Port and the specification used by the I-Cube Development System Software for proper bit stream generation. Legend: Ax -Switch Matrix Signal Px -I/O Port Signal IE -Input Enable OE -Output Enable CLK -Clock CKE - Clock Enable
Delay
E
REG
E CK
E
IE
LAT
I/O Port
NC BR
NC
Switch Matrix
LAT
CK E
REG
E
CLK CKE OE
Figure 4. Programmable I/O Port
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IQX Family Data Sheet
Symbol
Px Ax
I/O Port Function Input - The external signal is buffered from the I/O Port pin to the corresponding Switch Matrix line. In this mode an optional input enable (IE) can be selected. Either polarity can be selected for IE. The default level is a logic 1. Registered Input (with variable length shift register and inversion) - The external signal at the I/O Port pin is registered into a 7-bit edge-triggered shift register within the I/O Port. An 8-to-1 mux selects either the input (bit 0) or one of the 7 output bits of the shift register and connects it to the corresponding signal line in the Switch Matrix through a register. Any tap on the shift register can be selected. The true or complement of the incoming signal can be selected. The default is bit 0, true value. A clock source is required in this mode. Either edge of CLK can be selected. The default for CLK is rising edge. A clock enable (CKE) and input enable (IE) are also available but not required. Either polarity can be selected for IE and CKE. The default level for IE and CKE is a logic 1. The outputs of the shift register are unknown after hardware reset (TRST* = 0). Latched Input - The external signal at the I/O Port pin is latched by a level-sensitive flip-flop within the I/O Port. A latch enable source is required in this mode. The latch enable source is composed of CLK and CKE, and at least one must be specified. An input enable (IE) is also available but not required. Either polarity can be selected for CLK, CKE and IE. The default level for all three is a logic 1. The output of the flip-flop is unknown after hardware reset (TRST* = 0). Output - The internal signal is buffered from the corresponding Switch Matrix line to the I/O Port pin. In this mode an optional output enable (OE) can be selected. Either polarity can be selected for OE. The default level is a logic 0.
Mnemonic IN
IE IE 0 1 0 Px CLK CKE CE 0 7 7 DQ Ax
RI& [bit = value]& [INV = value]
LI
Px CLK
D LE
Q IE
Ax
CKE
OP
Ax
Px
OE
Ax CLK
D LE
Q
Px
CKE
OE
Latched Output- The internal signal on the Switch Matrix line is latched by a level-sensitive flip-flop within the I/O Port. A latch enable source is required in this mode. The latch enable source is composed of CLK and CKE, and at least one must be specified. An output enable (OE) is also available but not required. Either polarity can be selected for CLK and CKE. The default level for both is a logic 1. Either polarity can be selected for OE. The default level is a logic 0. The output of the flip-flop is unknown after hardware reset (TRST* = 0). Registered Output - The internal signal on the Switch Matrix line is registered by an edgetriggered flip-flop within the I/O Port. A clock source is required in this mode. Either edge of CLK can be selected. The default for CLK is rising edge. A clock enable (CKE) and output enable (OE) are also available but not required. Either polarity can be selected for CKE and OE. The default level for CKE is a logic 1 and the default level for OE is a logic 0. The output of the flip-flop is unknown after hardware reset (TRST* = 0). Bidirectional Transceiver - In this mode, the I/O buffer acts as a bidirectional transceiver between the I/O Port pin and the corresponding Switch Matrix line. This mode requires an input enable (IE) and output enable (OE). Either polarity can be selected for each but the default level for IE is a logic 1 and the default level for OE is a logic 0. When the same source (with default polarities) is used for IE and OE, it effectively acts as direction control. When the same control signal (with one polarity inverted) is used for IE and OE, it effectively acts as a Bus Repeater (BR) (see below) when both are enabled, and as No Connect (NC) when neither is enabled.
LO
RO
Ax CLK CKE
D
Q OE
Px
CE
IE
BT
Px
Ax
OE
Table 1. Summary of Programmable I/O Attributes for IQX Devices
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IQX Family Data Sheet
Symbol I/O Port Function Bidirectional Transceiver with Latched Input - This mode combines Latched Input (LI) and output buffer (OP). A latch enable source is required in this mode. The latch enable source is composed of CLK and CKE, and at least one must be specified. Either polarity can be selected for CLK and CKE. The default level for both is a logic 1. This mode also requires an input enable (IE) and output enable (OE). Either polarity can be selected for IE and OE. The default level for IE is a logic 1 and the default level for OE is a logic 0. The output of the flip-flop is unknown after hardware reset (TRST* = 0). Mnemonic BT&LI
Px
OE D Q IE
Ax
CLK LE CKE
0 OE 0 Px 0 7 1 7 DQ IE
Bidirectional Transceiver with Registered Input - This mode combines Registered Input with programmable tap and inversion (RI) and buffered Output (OP). A clock source is required in this mode. Either edge of CLK can be selected. The default for CLK is rising edge. A clock Ax enable (CKE) is available but not required. Either polarity can be selected. The default level for CKE is a logic 1. This mode also requires an input enable (IE) and output enable (OE). Either polarity can be selected for each. The default level for IE is a logic 1 and the default level for OE is a logic 0. The output of the flip-flop is unknown after hardware reset (TRST* = 0).
BT&RI& [bit = value]& [INV = value]
CLK CKE CE
Ax
IE D Q OE
Px
CLK LE CKE
Bidirectional Transceiver with Latched Output - This mode combines Latched Output (LO) and input buffer (IN). A latch enable source is required in this mode. The latch enable source is composed of CLK and CKE. At least one must be specified. Either polarity can be selected for CLK and CKE. The default level for both is a logic 1. This mode also requires an input enable (IE) and output enable (OE). Either polarity can be selected for IE and OE. The default level for IE is a logic 1 and the default level for OE is a logic 0. The output of the flip-flop is unknown after hardware reset (TRST* = 0).
BT&LO
Ax
IE D Q OE
Px
CLK CKE CE
Bidirectional Transceiver with Registered Output - This mode combines Registered Output (RO) and buffered Input (IN). A clock source is required in this mode. Either edge of CLK can be selected although the default is rising edge. A clock enable (CKE) is available but not required. Either polarity can be selected but the default level is a logic 1. This mode also requires an input enable (IE) and output enable (OE). Either polarity can be selected for IE and OE. The default level for IE is a logic 1 and the default level for OE is a logic 0. The output of the flip-flop is unknown after hardware reset (TRST* = 0).
BT&RO
IE 0 1 0 Px CLK CKE CE Q O DO OE 0 7 7 DI QI Ax
Bidirectional Transceiver with Registered I/O- This mode is a combination of Registered Input (RI) with programmable tap and inversion, and Registered Output (RO). A clock source is required in this mode. Either edge of CLK can be selected. The default is rising edge. A clock enable (CKE) is available but not required. Either polarity can be selected for CKE. The default level is a logic 1. This mode also requires an input enable (IE) and output enable (OE). Either polarity can be selected for IE and OE. The default level for IE is a logic 1 and the default level for OE is a logic 0. The output of the flip-flops is unknown after hardware reset (TRST* = 0).
BT&RI& [bit = value]& [INV = value] &RO
Other BT Modes- Other combinations of I/O Port modes (not covered in this table) are less likely but can be used. The mnemonic is BT [&RI | &LI] [&RO | &LO], where the specification inside the brackets "[ ]" is optional and "|" stands for either or. Insure that control signal requirements are met. In these modes, the output of the flip-flops is unknown after hardware reset (TRST* = 0).
Table 1. Summary of Programmable I/O Attributes for IQX Devices (Continued)
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IQX Family Data Sheet
Symbol I/O Port Function Bus Repeater - In the Bus Repeater mode, the I/O Port behaves as a wire (with a non-zero propagation delay). This unique feature patented by I-Cube incorporates a self-sensing circuit to determine signal direction and does not require a direction control signal. When multiple I/O Ports, configured as "Bus Repeater", are connected together through the Switch Matrix to form a single internal node, an (open collector or tristatable) external signal appearing at any one of the I/O Ports gets repeated (or broadcast) to other I/O Ports. The Bus Repeater mode requires a pull-up current source (see section on "Programmable Pull-Up Current") to operate properly. For more details, refer to the Technical Note: "The Bus Repeater Mode." Array Side Force 0 - In this input mode, the Switch Matrix line is forced low (logic 0), regardless of the signal on the corresponding I/O Port. In this mode an optional input enable (IE) can be selected. Either polarity can be selected for IE. The default level is a logic 1. Mnemonic BR
Px
Ax
A0
Px
Ax
Px
Ax
Array Side Force 1 - In this input mode, the Switch Matrix line is forced high (logic 1), regardless of the signal on the corresponding I/O Port. In this mode an optional input enable (IE) can be selected. Either polarity can be selected for IE. The default level is a logic 1. Pin Side Force 0 - In this output mode, the I/O Port pin is forced low (logic 0), regardless of the signal on the corresponding Switch Matrix line. In this mode an optional output enable (OE) can be selected. Either polarity can be selected for OE. The default level is a logic 0.
A1
F0
Ax
Px
Ax
Px
Pin Side Force 1 - In this output mode, the I/O Port pin is forced high (logic 1), regardless of the signal on the corresponding Switch Matrix line. In this mode an optional output enable (OE) can be selected. Either polarity can be selected for OE. The default level is a logic 0.
F1
Px
Ax
No Connect - In this mode, the I/O Port pin is isolated from the Switch Matrix. This is done by tristating both the input and output part of the I/O buffer.
NC
Table 1. Summary of Programmable I/O Attributes for IQX Devices (Continued)
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IQX Family Data Sheet
1.3 I/O Control Signals
The IQX family has a structure that gives the user a lot of flexibility in controlling the behavior of each I/O Port. As shown in Figure 6 and described below, Clock (CLK), Clock Enable (CKE), Input Enable (IE) and Output Enable (OE) signals for each I/O Port can be selected from multiple sources. The control polarity can also be individually selected.
PORTX+1 IOBX+1 13 GC0-GC12 13 GT0-GT12
0-12 13 14 15 SEG 3
SEG 2
0 1
CLKX
Common to All I/O Ports
0-12 13 14 15
0 1
CKEX
SEG 0
5 COUNTER K0/KCLK K1/KCKE K2/KRST K3/KCLR
KCLK KCKE KRST KCLR
K0-K4
0
0-12 13 14 15
0 1
IEX
5 Count 5 5
1 1111 1 0 1
SEG 1 0-12 13 14 15
0 1
K4/K1F
5-Bit Terminal Count
OEX
Match = 1
From Mode Control Register
C O M P A R E
5
SEG 4
5-Bit Tag
PORTX IOBX
GC Bus GT Bus KEY Bus
= Programming Bits = External Pins
IOBX-1
Included in Each I/O Ports
Figure 6. I/O Control 14 Revision 5.0 June 2000
IQX Family Data Sheet
1.3.1 Clock Control An I/O Port can be individually programmed to select its clock (CLK) and clock enable (CKE) signals from sixteen sources. The source can either be the two (four for IQX320 only) dedicated pins - GC0 and GC1 (GC0 through GC3 for IQX320), 11 (9 for IQX320) clock pins that are shared with signal I/O pins - GC2 through GC12 (GC4 through GC12 for IQX320), the nearest neighboring I/O Port, or the MATCH signal generated using Key Control (K0 - K4) pins. 1.3.2 Tristate Control An I/O Port can be individually programmed to select its Input Enable (IE) and Output Enable (OE) signals from sixteen signals. The source can either be the four (five for IQX320 only) dedicated tristate pins - GT0 through GT3 (GT0 through GT4 for IQX320), nine (eight for IQX320) tristate pins that are shared with signal I/O pins - GT4 through GT12 (GT5 through GT12 for IQX320), the nearest neighboring I/O Port, or the MATCH signal generated using Key Control (K0 - K4) pins. 1.3.3 Neighboring I/O Port As A Control Source A physically adjacent I/O Port on the die can be used as a source for any of the I/O control signals. Port 1 is the control source for Port 0, Port 2 is the control source for Port 1 and so on. Port 0 is the control source for the highest number I/O Port on the device die. Note that due to bondout restrictions the neighboring I/O Port may not always be brought out to a package pin on the IQX240B and IQX128B devices. 1.3.4 Key Control Pins as a Control Source The Key Control feature on the IQX devices allows the user to encode mutually exclusive control signals for use as I/O control signals. The Key pins, K0 through K4 are shared with I/O Ports. This feature, shown schematically in Figure 6, works as follows: Each I/O Port contains a 5-bit tag which can be programmed with a unique value when the I/O Ports are configured. A comparator in each I/O Port continuously compares the programmed tag value with the signals present on the Key pins or the output of the internal 5-bit counter. The output of the comparator, which produces a logic 1 on a match, can be selected as a control signal. The Key Control is intended for use with level sensitive signals such as IE, OE, CKE (in registered modes only). If Key Control is used in situations where a short glitch on the internal "Match" signal is unacceptable (i.e., using the Key Port for CLK in registered modes and CLK and/or CKE in latched modes), it is recommended that one of the Key pins be used as a qualifier and its value changed after the other Key pins have stabilized to prevent glitches on the internal "Match" signal. Note that when key match is used as Output Enable (OE) the match will disable the driver, while a non-match will enable it. This can be reversed by configuring the I/O Port to use reverse polarity for OE. Depending on the value of the Counter Enable bit in the Mode Control Register (see Table 10, the key input to the 5-bit comparator comes either directly from the Key Pins (K0 through K4) or from the output of an internal 5-bit up counter. If the counter is selected by setting the Counter Enable bit to a logic 1, the Key pins serve as control inputs to the counter as described below. K0/KCLK - Counter Clock input K1/KCKE - Counter Clock Enable K2/KRST - Counter (Synchronous) Reset K3/KCLR - Counter (Asynchronous) Clear K4/K1F - Counter Select "1F" Hex The counter is a 5-bit modulo up counter controlled by the rising edge on the counter clock pin (KCLK). It counts up to the 5-bit value programmed in the Mode Control Register and then resets to zero on the following clock edge. KCKE pin is used to qualify the clock. Clocking is enabled when KCKE is high and disabled when low. When the K1F pin is asserted (high), the output of the counter is forced to "11111" regardless of the internal count. During this time the counter continues to count up in response to the clock input. When the KRST pin is asserted, the counter is reset on the following clock edge. KCLR on the other hand is an asynchronous clear. When asserted, the counter is immediately reset to zero. When the device is reset, the Counter Enable bit and the five Count Value bits are reset to zero. 1.3.5 Default Values for Control Signals When the device is reset all I/O Ports are set to the default configuration of flow-through input (IN), This is achieved by setting the 16-to-1 muxes shown in Figure 6, to select input 15 (Vss); while the 2-to-1 muxes used for polarity selections are set to select non-inverted value for Clock (CLK) and Clock Enable (CKE), and inverted value for Input Enable (IE) and Output Enable (OE).
1.4 RapidConfigure (RC) Interface
The RapidConfigure (RC) Interface allows Switch Matrix connections and I/O Port configurations to be changed quickly. A single Switch Matrix connection can be made or broken in a single RapidConfigure cycle; while a single I/O Port or group of
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IQX Family Data Sheet
2, 4, 8 or 16 I/O Ports (having the same configuration) can be configured in a minimum of one or maximum of eight RapidConfigure cycles. The RapidConfigure interface shown in Figure 7 is a write only interface. Its operation is some what similar to a memory write cycle in a microprocessor system - it uses address, data and control signals to write to the Switch Matrix SRAM cells and I/O Port configuration registers. The Control bus, {P/S (Port/Switch), C[1:0]} defines the type of operation performed by the RapidConfigure cycle, while the Row Address, RA[m-1:0], and Column Address, CA[m-1:0], provide the necessary addresses and/or data for the different operations. The value "m" is different for different devices as shown in Table 2. WE (Write Enable) acts as chip select while STROBE is the write strobe.
Feature Total Number of I/O Ports I/O Ports Used for RC Interface1 Row Address and Column Address Bus Widths I/O Ports whose connections can be changed using RC interface2 IQX320 320 23 / 22 9 IQX240B 240 23 / 22 9 IQX160 160 21/20 8 IQX128B 128 19/18 7
In a typical system, an embedded processor will compute the required Row Address, Column Address and Control values and apply them to the IQX device. Alternatively, these values could be computed before hand using the I-Cube supplied development system software (IDS100), and stored in a lookup table. The RapidConfigure mode is enabled or disabled by correctly setting the RC bit in the Mode Control Register. Table 3 shows the different RapidConfigure options, depending on the values of the "RC" and "RM" bits in the Mode Control Register. During hardware reset (TRST* = 0) these bits are set to the signal value on the "RCE" (RapidConnect Enable) pin. The values of these bits can then be changed if required using the JTAG serial interface. Note that the "P/S" signal shown in Figure 7 is required only if the RapidConfigure interface is used for changing I/O Port configuration, i.e., when RC bit = 1 and RM bit = 1. The pin is available for use as signal I/O pin (I/O Port) when RM bit = 0. Table 8 summarizes the different options. Compatibility with the IQ family devices is achieved by connecting the RCE pin to VSS on the board.
RC Bit RM Bit Operation RapidConfigure Mode is disabled. The device can only be configured using the JTAG-based serial interface. In this mode, the I/O Ports used for RapidConfigure Interface can be used for as signal I/O Ports. RapidConfigure Mode is enabled for changing Switch Matrix connections but not for I/O Port configuration. The I/O Ports can only be configured using the JTAG-based serial interface. In this mode, the signal coming from the P/S pin is forced low internally. The P/S pin is available as a signal I/O Port. RapidConfigure Mode is enabled for changing Switch Matrix connections and I/O Port configurations.
298
218
140
102
0
0
1
0
Table 2. RapidConfigure Interface Pin Count
Notes:
1. The IQ compatibility mode uses the lower of the two numbers shown.
2. Due to the requirements for compatibility with the IQ Family and/or bondout restrictions, this number is lower than (# in row 1 - # in row 2) for some devices.
ADDRESS BUS
1
1
Table 3. RapidConfigure Options
DATA BUS
CA[m-1:0]
I/O Port I/O Port
RA[m-1:0]
IQX CPU
RCE C0 C1 P/S WE STROBE TRST* TDI TMS TCK Optional
The user must ensure that the I/O Ports used for the RapidConfigure interface are in the Input (IN) mode and any connections to corresponding signal lines in the Switch Matrix are cleared before attempting to configure the device using this interface. During device reset, the I/O Ports used for the RapidConfigure interface are set to the required Input (IN) and all connections in the Switch Matrix are cleared. 1.4.1 Switch Matrix Connection Changes
CLK
Config Control Logic
I/O Port
Figure 7. IQX RapidConfigure System Interface
As indicated earlier, the Switch Matrix SRAM cells that control the connections among I/O Ports form a two dimensional array. Every SRAM cell location in the Switch Matrix that is being written to is uniquely identified by its Row (or Word) Address and Column (or Bit) Address. The real SRAM cell responsible for the connection between two I/O Port numbers "i" and "j" on the
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IQX Family Data Sheet
device die has the Row Address of Binary (i) and Column Address of Binary (j), or vice versa. Furthermore, when dealing with the bondout devices IQX240B and IQX128B the I/O Port numbers on the device package must first be mapped to the I/O Port number on the device die to determine the Row and Column Address of the real SRAM cell. Refer to Appendix A for the tables and decision logic used to determine the location of the real SRAM cell, and the mapping of I/O Port numbers on the device package to I/O Port numbers on the device die. The Control bus, {P/S=0, C[1:0]} specifies the type of connection change, either make or break; the Row and Column Addresses are the values corresponding to the two I/O Port numbers as determined using the tables in Appendix A. P/S is set to 0 when changing Switch Matrix connections using RapidConfigure. As indicated in Table 4, when the control bit C1 is held low during a make or break operation, the remaining SRAM cells belonging to the word addressed by the Row Address are automatically cleared. This feature can be used to speed up connection changes as described below. In one common crossbar application, the signal I/O Ports on the device are divided into equal groups of inputs and outputs, and a pin in the output group is required to be connected to any pin in the input group. By judicious assignment of the I/O Ports to the output group, one can ensure that for every output port, the real SRAM cells controlling the connection between that output port and all ports in the input group fall on the word corresponding to the output port number. With this assignment, when establishing a new connection using RapidConfigure, any existing connection to that output I/O Port is automatically broken (C1=0). Thus a connection change, i.e., breaking an existing connection and then making a new one, can be accomplished in one RapidConfigure cycle. Tables in Appendix A provide information on determining the word locations of real SRAM cells. Refer to ICube's application notes for further details of using RapidConfigure. Attempting to alter the contents of the SRAM cells responsible for connections to the I/O Ports used for the RapidConfigure Interface will result in unpredictable results.
Operation Break the connection between I/O Ports i & j by writing a "0" to the SRAM cell location whose Row Address is i and Column Address is j, [0 i, j r]. Other SRAM cells are unchanged, i.e., no other connections are affected.(2,3) Make the connection between I/O Ports i & j by writing a "1" to the SRAM cell location whose Row Address is i and Column Address is j, [0 i, j r]. Other SRAM cell are unchanged, i.e., no other connections are affected.(2,3) Break the connection between I/O Ports i & j by writing a "0" to the SRAM cell location whose Row Address is i and Column Address is j, [0 i, j r]. Clear all SRAM cells on row i; i.e., break all the connections controlled by the real SRAM cells belonging to row i.(2,3) Make the connection between I/O Ports i & j by writing a "1" to the SRAM cell location whose Row Address is i and Column Address is j, [0 i, j r]. Clear all SRAM cells on row i; i.e., break all the connections controlled by the real SRAM cells belonging to row i.(2,3)
Control Bus {P/S, C[1:0]} 010
Row Address RA[m-1:0] BINARY(i)
Column Address CA[m-1:0] BINARY(j)
011
BINARY(i)
BINARY(j)
000
BINARY(i)
BINARY(j)
001
BINARY(i)
BINARY(j)
Table 4. Changing Switch Matrix Connections Using RapidConfigure
Notes:
(1) Binary (j) is the m-bit binary equivalent value of i. Right most bit is LSB. m equals Row/Column Address width. "i" and "j" refer to the I/O Port number on the device die. (2) "r" is the I/O Port number on the die corresponding the highest available signal I/O Port. (3) Assumes the real SRAM cell controlling the connection has Row Address=Binary(j)
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IQX Family Data Sheet
1.4.2 I/O Port Configuration Configuring I/O Ports using the RapidConfigure interface involves two steps. During the first step the 50-bit I/O Port Configuration Holding Register, consisting of seven 8-bit segments, is loaded with the configuration data. The loading is accomplished one 8-bit segment at a time, and may take up to 7 RapidConfigure cycles to load this register. In the second step, the data in the I/O Port Configuration Holding Register is completely transferred to the individual I/O Ports in a single RapidConnect cycle. A single I/O Port, or a group of 2, 4, 8 or 16 contiguous I/O Ports with a starting address of modulo 2, 4, 8 or 16 respectively, (and requiring the same configuration) can be configured in a single RapidConfigure cycle during this step. When using RapidConfigure for configuring I/O Ports, the Control bus, {P/S = 1, C[1:0]} specifies the type of operation; and the Row and Column Addresses provide the information about
IQX320, IQX240B Operation Load Configuration Register (1) Configure Port i [0 i r] (2,3) Configure 2 I/O Port Group Configure 4 I/O Port Group Configure 8 I/O Port Group Configure 16 I/O Port Group Control Bus {P/S, C[1:0]} 110 111 111 111 111 111 Row Add. RA[8:0] 000000sss ppppppppp pppppppp0 ppppppp00 pppppp000 ppppp0000 Col. Add. CA[8:0] 0dddddddd 000000001 000000011 000000111 000001111 000011111
the I/O Port, or the group of ports to be configured. P/S is set to 1 when configuring I/O Ports using RapidConfigure. Refer to Table 5 for details. The I/O Port information specified in the Row and Column address values applies to the I/O pad location on the die. When using the RapidConfigure interface for configuring bondout versions such as the IQX240B and IQX128B proper translation for I/O Port number on the package to the corresponding I/O Port number on the die must first be made. Refer to Appendix A for the mapping. I/O Ports used for the RapidConfigure interface P/S, C[1:0], RA, CA, WE and STROBE, cannot be configured using the RapidConfigure interface. Combinations not listed in Table 5 may result in unpredictable results and should be avoided.
IQX160 Row Add. RA[7:0] 0000sssd pppppppp ppppppp0 pppppp00 ppppp000 pppp0000 Col. Add. CA[7:0] 0ddddddd 00000001 00000011 00000111 00001111 00011111
IQX128B Row Add. RA[6:0] 000sssd ppppppp pppppp0 ppppp00 pppp000 ppp0000 Col. Add. CA[6:0] ddddddd 0000001 0000011 0000111 0001111 0011111
Table 5. Configuring I/O Ports Using RapidConfigure Interface
Notes:
(1) "sss" is the 8-bit segment in the 50-bit I/O Port Configuration Holding Register and dddddddd is the 8-bit data to be loaded. Right most bits are LSBs. (2) "ppppp...." is the I/O Port or I/O Port Group number to be configured. This vector is 9-bits long or less, depending on the device and size of the I/O Port Group. The I/O Port Group is a contiguous group of I/O Ports with the lowest I/O Port number being (ppppp....) multiplied by (Number of Ports in the Group). (3) "r" is the I/O Port number on the die corresponding to the highest I/O Port number on the package that can be configured using RapidConfigure.
1.4.3 I/O Port Configuration Holding Register I/O Port Configuration Holding Register is used to hold the data that is to be loaded into the I/O Port Configuration Register. This 50-bit holding register consists of six 8-bit segments and one 2bit segment, and is loaded one segment at a time using the RapidConfigure interface. Using the RapidConfigure interface, the holding register is first loaded with 50 bits of data that defines the I/O Port function. The data is then transferred into the I/O Port Configuration Register(s), also using the RapidConfigure interface. Depending on the current contents of the holding register segments, it may take 7 RapidConfigure cycles or less to load the holding register. The holding register contains unknown values when the device is reset. Table 6 describes the I/O Port programming bits and shows their location in the I/O Port Configuration Holding Register. Table 7 shows the bit values for the various I/O Port configurations.
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IQX Family Data Sheet
Name IES0 IES1 IES2 IES3 INV_IE IN A0 A1 OES0 OES1 OES2 OES3 INV_OE OP F0 F1 CLKS0 CLKS1 CLKS2 CLKS3 LO LI RO RI
Seg# 0
Bit# 0 1 2 3 4 5 6 7
Group Function Input Group
Reset Value 1 1 1 1 1 1 0 0 Input Enable (IE) Source Bit 0 (LSB). Input Enable (IE) Source Bit 1. Input Enable (IE) Source Bit 2. Input Enable (IE) Source Bit 3 (MSB).
Description
Invert Polarity for Input Enable; Default is Active High. Input Port Mode. Force Array Side Low. Force Array Side High. Output Enable (OE) Source Bit 0 (LSB). Output Enable (OE) Source Bit 1. Output Enable (OE) Source Bit 2. Output Enable (OE) Source Bit 3 (MSB). Invert Polarity for Output Enable, Default is Active Low. Output Port Mode. Force Pin Side Low. Force Pin Side High. Clock (CLK) Source Bit 0 (LSB). Clock (CLK) Source Bit 1. Clock (CLK) Source Bit 2. Clock (CLK) Source Bit 3 (MSB). Latched Output Mode. Latched Input Mode. Registered Output Mode. Registered Input Mode.
1
0 1 2 3 4 5 6 7
Output Group
1 1 1 1 1 0 0 0
2
0 1 2 3 4 5 6 7
Clock Source, Register, and Latch Group
1 1 1 1 0 0 0 0
Table 6. I/O Port Configuration Bits
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IQX Family Data Sheet
Reset Value 1 1 1 1 1 0 0 0 Key Control and Pipeline Delay Group 0 0 0 0 0 0 0 0 Misc. Group 0 1 1 0 0 0 1 1 Test Group 0 0 Clock Enable (CKE) Source Bit 0 (LSB). Clock Enable (CKE) Source Bit 1. Clock Enable (CKE) Source Bit 2. Clock Enable (CKE) Source Bit 3 (MSB). Invert Polarity for Clock Enable; Default is enabled when high for Register and transparent when High for Latch. Invert Polarity for Clock; Default is Rising Edge Triggered for Register and Transparent when High for Latch. Invert Input Data in Registered Input (RI) mode. Reserved for internal use. Must be set to default value. Key Tag Bit 0 (LSB). Key Tag Bit 1. Key Tag Bit 2. Key Tag Bit 3. Key Tag Bit 4 (MSB). Input Pipeline Delay Bit 0 (LSB). Input Pipeline Delay Bit 1. Input Pipeline Delay Bit 2 (MSB). Bus Repeater Mode. Array Side Trickle Current. Pin Side Trickle Current. Weak Static Pull Up Current. Strong Static Pull Up Current. Non-Buffered Mode. Reserved for internal use. Must be set to default value. Reserved for internal use. Must be set to default value. Reserved for internal use. Must be set to default value. Reserved for internal use. Must be set to default value.
Name CKES0 CKES1 CKES2 CKES3 INV_CKE INV_CLK INV_PI reserved K0 K1 K2 K3 K4 DELAY0 DELAY1 DELAY2 BR IAS IPS PU_WK PU_SG NB reserved reserved reserved reserved
Seg# 3
Bit# 0 1 2 3 4 5 6 7
Group Function Clock Enable Group
Description
4
0 1 2 3 4 5 6 7
5
0 1 2 3 4 5 6 7
6
0 1
Table 6. I/O Port Configuration Bits (Continued)
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IQX Family Data Sheet
1.4.4 I/O Port Configuration Register Contents
I/O Mode Mnemon ic Seg 6 Bit 76543210 Seg 5 Bit 76543210
. . NB PU_SQ PU_WK IPS IAS BR
Seg 4 Bit 76543210
DELAY2 DELAY1 DELAY0 K4 K3 K2 K1 K0
Seg 3 Bit 76543210
. INV_PI INV_CLK INV_CKE CKES3 CKES2 CKES1 CKES0
Seg 2 Seg 1 Seg 0 Bit Bit Bit 76543210 76543210 76543210
F1 F0 OP INV_OE OES3 OES2 OES1 OES0 A1 A0 IN INV_IE IES3 IES2 IES1 IES0 RI RO LI LO CLKS3 CLKS2 CLKS1 CLKS0
Value After Reset Input Input w/ Tristate Latched Input Latched Input w/ Tristate Registered Input Registered Input w/ Tristate Output Output w/ Tristate Latched Output Latched Output w/ Tristate Registered Output Registered Output w/ Tristate Bidirectional Transceiver Bidirectional Transceiver w/ Latched Input Bidirectional Transceiver w/ Registered Input Bidirectional Transceiver w/ Latched Output Bidirectional Transceiver w/ Registered Output Pin Force 0 Pin Force 1 Array Force 0 Array Force 1 Bus Repeater No Connect BT BT&LI BT&RI BT&LO BT&RO F0 F1 A0 A1 BR NC RO LO OP RI LI IN
. . . . . . . .
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
11000110 11000110 11000110 11000110 11000110 11000110 11000110 11000110 11000110 11000110 11000110 11000110 11000110 11000110 11000110 11000110 11000110 11000110 11000110 11000110 11000110 11000110 110**111 11000110
00000000 00000000 000***** 000***** 000***** ******** ******** 00000000 000***** 000***** 000***** 00000000 000***** 00000000 000***** 000***** 000***** 000***** 00000000 00000000 00000000 00000000 00000000 00000000
00011111 00011111 00011111 00****** 00****** 0******* 0******* 00011111 00011111 00****** 00****** 00****** 00****** 00111111 00****** 00****** 00****** 00****** 00011111 00011111 00011111 00011111 00011111 00011111
00001111 00011111 00111111 00001111 00011111 00111111 00001111 00011111 001***** 0010**** 00011111 00111111 0010**** 00011111 001***** 1000**** 00011111 00011111 1000**** 00011111 00001111 00001111 00101111 000***** 00001111 001***** 00001111 0001**** 00101111 00001111 0001**** 001***** 00001111 0100**** 00001111 00001111 0100**** 000***** 00001111 00001111 001***** 001***** 0010**** 001***** 001***** 1000**** 001***** 000***** 0001**** 001***** 001***** 0100**** 000***** 001***** 00001111 01001111 00001111 00001111 10001111 00001111 00001111 00011111 01011111 00001111 00011111 10011111 00001111 00101111 00111111 00001111 00011111 00001111
Table 7. I/O Configuration Register Contents
Note:
* User defined value
Each programmable I/O Port on the IQX device contains a 50-bit Configuration Register. The function of an I/O Port is determined by the contents of its configuration register. Table 7 shows the contents for the different I/O functions. Combinations that are not listed are illegal and may result in improper operation or damage to the device. The bits in Table 7 indicated by a "*" refer to the values and polarity of the various control sources and must be filled in correctly based on the user selection of the control sources. 1.4.5 Reset Commands The RapidConfigure interface can also be used to quickly clear the Switch Matrix and reset the I/O Ports to their default state. Refer to the table below for details. When RapidConfigure is used for resetting the I/O Ports the contents of the configuration
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holding register are set to the default state shown in Table 8, however the contents of the Mode Control Register and the state of the JTAG controller are not affected.
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IQX320, IQX240B Operation Clear All Switch Matrix SRAM Cells (Break Connections) Clear All Switch Matrix SRAM Cells (Break Connections) and Set All I/O Ports to Power-on Default Function [Input (IN)] Control Bus (P/S, C[1:0]) 111 Row Add. RA[8:0] 000000000 Col. Add. CA [8:0] 000100000
IQX160 Row Add. RA[7:0] 00000000 Col. Add. CA[7:0] 00100000
IQX128B Row Add. RA[6:0] 0000000 Col. Add. CA[6:0] 0100000
111
000000000
001100000
00000000
01100000
0000000
1100000
Table 8. RapidConfigure Reset Commands
1.5 JTAG-based Configuration Controller
In the IQX devices, the I/O attributes and Switch Matrix connections can be programmed using the JTAG serial bus. Additionally, the RapidConfigure Interface, used for quickly changing I/O Port Configurations and Switch Matrix connections, can be enabled or disabled using the JTAG serial bus. The JTAG-based serial mode is always available for configuration regardless of whether the RapidConfigure mode is enabled or disabled. However proper care must be taken when switching between JTAG and RapidConfigure for configuring the devices. The user must ensure that the RapidConfigure mode is first disabled by using JTAG serial mode to set the RC bit to zero in the Mode Control Register before attempting to change Switch Matrix connections or I/O Port configuration through JTAG. In most cases, the user does not need to know the details of the JTAG protocol. The I-Cube supplied software will automatically generate the necessary bit stream from a higher-level textual description of the required configuration. 1.5.1 JTAG Interface The JTAG interface is a serial interface and uses five pins: Test Data In (TDI), Test Data Out (TDO), Test Clock (TCK), Test Mode Select (TMS) and Test Reset (TRST*). TCK is used to clock data in and out of TDI and TDO. TMS, in conjunction with TDI implements a state machine that controls the various operations of the JTAG protocol. Data on the TDI and TMS pins is clocked into the IQX device on the rising edge of the TCK signal, while the valid data appears on the TDO pin after the falling edge of TCK. On the IQX devices, TRST* is used to reset both the device and the JTAG controller.
1.5.2 I/O Port Configuration I/O Port configuration is accomplished by loading the appropriate bit stream into the programming registers present at each I/O Port. The JTAG serial bus is used to load configuration data into the I/O Port programming registers, one I/O Port at a time. 1.5.3 Switch Matrix Configuration The contents of the SRAM cells controlling Switch Matrix connections can be modified using the JTAG. This is accomplished by loading the configuration data, one word at a time into the SRAM cells in the Switch Matrix. 1.5.4 Mode Control Register Configuration The IQX device contains a Mode Control Register. Some bits in the register are used to store user flags such as RapidConfigure Enable, and certain non-user flags required for proper functioning of the device. The contents of this register can be changed using the JTAG interface. Refer to Table 10 for details.
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IQX Family Data Sheet 2.0 MISCELLANEOUS DETAILS
2.1 Device Reset
To ensure proper operation, the device reset pin, TRST* must be held low during power up. The reset pulse must be at least 200 ns long. The IQX device is ready for configuration as soon as it comes out of reset. The recommended reset circuitry is shown in Figure 8, using an external supervisor device. . It should be noted that the TRST* pin must not be driven by any devices which cannot guarantee a low signal during power-up. Improper devices are those whose pins are either high or tristated during power-up. Examples of such devices are SRAMbased FPGAs. When the device is in operation, different functional blocks can be reset using one of following methods. Each method performs a slightly different action as shown in Table 9. In any of the reset methods the edge and level-sensitive flipflops in the I/O Port buffers are not cleared and will have unknown output values.
IQX
+5 Vmon Supervisor Vdd Ref GND RST RST PBRST TRST*
Figure 8. Reset Circuit
I/O Config. Holding Register JTAG State Machine
Reset Method Pulsing TRST* low Shifting in the "Device Reset" instruction using JTAG Applying "I/O Port and Switch Matrix Reset" instruction using RapidConfigure interface Applying "Switch Matrix Reset" instruction using RapidConfigure interface
Switch Matrix Cleared Cleared Cleared Cleared
I/O Ports
RapidConfigure Interface Enabled if RCE pin = 1
Set to Input (IN) Set to Input (IN) Reset
Set to Input (IN) Set to Input (IN) Unchanged Enabled if RCE pin = 1 Set to Input (IN) Set to Input (IN) Unchanged Stays Enabled Unchanged Unchanged Unchanged Stays Enabled
Table 9. Device Reset
2.2 Mixed Voltage Operation
There are multiple sources for power on the IQX device. The first one called VDD is a 5V source and is used to power the device core, including the Switch Matrix SRAM cells, I/O Port logic (excluding the I/O buffer driver), I/O control logic, JTAG logic and other circuitry. The I/O buffer drivers are powered by a different source called VDD.PAD. The number of VDD.PAD sources depends on the device. Table 13 shows the number of VDD.PAD sources and the I/O Ports controlled by them. The VDD.PAD pins can be connected to either a 5V or 3V supply. This makes it easy to interface IQX device to 5V and/or 3V logic levels.
2.3 Power Pin VDD.X
The IQX devices contain a pin marked VDD.X. The devices contain an on-chip charge pump. In order for the charge pump to operate correctly, it is required that the VDD.x pin be left floating and completely unconnected. The charge pump should also be left in its default "on' setting. This is controlled by bit #6 (C_PUMP) of the mode control register.
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2.4 Mode Control Register
The IQX device contains a 16-bit Mode Control Register. It stores the RapidConfigure Enable and certain other non-user flags which must be set correctly for the proper functioning of the device. Table 10 shows the bit assignment and their function.
Bit # 0 Name KCNT Default 0
A special JTAG instruction is used to write to the Mode Control Register. When this register is written using JTAG the least significant bit (Bit 0) is shifted in first.
Description Key Counter Enable. When set, uses the internal 5-bit counter to provide Key Address Used to enable IOB configuration through RapidConfigure interface. Default value equals the RCE pin value on Reset. Enables or disables RapidConfigure mode. Default value equals the RCE pin value on Reset. IOB Pull Up 10k Ref BR external one-shot Pulse Width 10k Ref BR internal one-shot Pulse Width 10k Ref Charge Pump Enable Bit IOB Pull Up 20k Ref BR external one-shot Pulse Width 20k Ref BR internal one-shot Pulse Width 20k Ref For internal use. Should not be changed by the user. Terminal count value bit 0 (LSB) when internal counter is used as Key Address Terminal count value bit 1 when internal counter is used as Key Address Terminal count value bit 2 when internal counter is used as Key Address Terminal count value bit 3 when internal counter is used as Key Address Terminal count value bit 4 (MSB) when internal counter is used as Key Address
1
RM
*
2 3 4 5 6 7 8 9 10 11 12 13 14 15
RC IOB_PU1 BRO_PW1 BRI_PW1 C_PUMP IOB_PU2 BRO_PW2 BRI_PW2 INTERNAL KVAL0 KVAL1 KVAL2 KVAL3 KVAL4
* 1 1 1 1 0 0 0 0 0 0 0 0 0
Table 10. Mode Control Register Bit Assignment
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IQX Family Data Sheet 3.0 IN SYSTEM CONFIGURATION USING JTAGBASED CONFIGURATION CONTROLLER
The JTAG-based configuration mode allows the user to initialize the device, configure the I/O Ports, establish connections through the Switch Matrix and set the contents of the Mode Control Register. Configuring the device using JTAG involves two steps. In the first step the user generates the bit stream. Two different software options - off-line and embedded bit stream generation are available to accomplish this task. The choice depends on the target application. The second step is the actual downloading of the bit stream into the device. The downloading circuitry can take on different forms, depending on the target application.
3.1 Bit Stream Generation
The configuration bit stream can be generated off-line or insystem by an embedded CPU using one of the following methods: * By using I-Cube Development System Software product IDS100. * By user written code based on the information provided in the "IQX Family Register Programming Users Reference." If the bit stream is generated off-line then, depending on the application, it is either stored in non-volatile memory or directly downloaded from a host processor such as a PC connected to the target hardware. The software used for off-line generation accepts a text file describing the desired configuration - connections between different I/O Ports, functional attributes of each I/O Port, and settings of certain user flags - and generates a file containing the bit stream.
Create Configuration File (Text File)
Compile Configuration File to Create Configuration Bitstream
3.2 Bit Stream Downloading
The bit stream can be downloaded into the IQX device using several different hardware schemes. The choice depends on the end application. All these schemes use the standard JTAG protocol and timing. As per the JTAG protocol, the clock signal (TCK) must be supplied externally. If the target hardware is controlled by a computer such as a PC, the parallel port on the computer can be used to download the bit stream. I-Cube provides a software utility to perform the downloading. Under this scheme, the necessary data for TDI and TMS pins as well as the (software generated) TCK clock signal are sent over the parallel port. An on-board byte-wide EPROM or E2PROM, or a serial E2PROM can be used to store the bit stream. Using minimal external logic, the bit stream stored in one of these devices can be downloaded into the IQX device(s) over the TDI and TMS pins, with the TCK pin used for synchronization. The clock signal for the TCK pin is generated by the external logic.
Convert Bitstream for Use with Configuration Circuitry in the Target System EPROM Serial Onboard Download EPROM Microcontroller Cable
Figure 9. Off-line Bit Stream Generation
Memory
Application Software IQX Programming Library
Configuration Circuitry
IQX
Figure 10. Embedded Bit Stream Generation
If the target system has an on-board microcontroller, the bit stream data can be read from memory and downloaded into the IQX device(s) using 3 I/O pins on the microcontroller to generate the required TDI, TMS and TCK signals. For real-time applications, the microcontroller/microprocessor can generate the bit stream (using the I-Cube supplied software examples or user written code) and then download it into the IQX device in a single operation.
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IQX Family Data Sheet
The actual time required to download the configuration bit stream and program a IQX device depends on the device(s) used, the user's specific configuration pattern, and JTAG clock frequency. Table 11 shows the number of JTAG cycles and configuration time required for some typical operations. The size of the memory (number of bytes) required is two (one each for TDI and TMS) times the number of JTAG cycles divided by eight.
U3 IQX TDI TDI TCK TMS TRST* TDO TDO
U2 IQX TDI TCK TMS TRST* TDO
U1 IQX TDI TCK TMS TRST* TDO
3.3 Configuring Multiple IQX Devices
The JTAG-based controller allows a single device or multiple IQX devices connected in a chain to be configured in a single operation. For multiple device configuration, the pins are connected as shown in Figure 11.
TCK TMS TRST*
Figure 11. Configuring Multiple IQX Devices
During the initial configuration sequence, the internal controllers on all IQX devices are first brought to their reset state by pulsing the TRST* reset pin low. This is followed by the actual configuration bit stream, which is downloaded into the IQX devices over the TDI and TMS pins.
IQX320 Bitstream Size JTAG Cycles Config. Time
IQX240B Bitstream Size JTAG Cycles Config. Time
IQX160 Bitstream Size JTAG Cycles Config. Time
IQX128B Bitstream Size 10 bits 84 bits 152 bits 2.5 KB 64 bits 372 bits 6 KB 9 KB JTAG Cycles 5 42 76 10 K 32 186 24 K Config. Time 500 ns 4.2 s 7.6 s 1.0 ms 3.2 s 18.6 s 2.4 ms 3.4 ms
Operation JTAG Reset Sequence (TMS = "11111") Enable or Disable Rapid Configure Change IOB attributes of ONE I/O Port Change IOB attributes of ALL I/O Ports Reset JTAG Controller + Reset ALL I/O Ports + Clear ALL SRAM cells Connect or disconnect two I/O Ports Configure Entire Switch Matrix 5
500 ns 4.2 s 7.6 s 2.4 ms 3.2 s 34.6 s
10 bits 84 bits 152 bits 6 KB 64 bits 692 bits 27.5 KB
5 42 76 18 K 32 346 84 K
500 ns 4.2 s 7.6 s 1.8 ms 3.2 s 34.6 s 8.4 ms
10 bits 84 bits 152 bits 4.5 KB 64 bits 692 bits
5 42 76 12 K 32 186
500 ns 4.2 s 7.6 s 1.2 ms 3.2 s 18.6 s 3.0 ms 4.2 ms
10 bits 84 bits 152 bits 4 KB 64 bits 372 bits 7.5 KB
42 76 24 K 32 346
110 K 11.0 ms
21 KB 30 K
Completely Configure the Device (All I/O and All Switch Matrix Connections) 134K
13.4 34 KB 102 K 10.02 26 KB 42 K ms ms
11 KB 34 K
Table 11. Number of JTAG Cycles and Configuration Time (using a 10 MHz JTAG Clock)
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IQX Family Data Sheet 4.0 PIN SUMMARY
IQX320 P000 - P259, P262, P264, P266, P274, P276, P278, P280, P282, P284, P286, P288, P290, P292, P294, P305 P260, P261, P263, P265, P267 IQX240B IQX160 IQX128B P000 - P083 DIR I/O Dedicated I/O Ports Description P000 - P193, P000 - P103, P225 P107, P113, P118, P119, P123, P124, P129, P130, P135, P136 P194, P195, P196, P197, P198 P199 - P203 P104, P105, P106, P108, P109 P110, P111, P112, P114, P115 P116, P117, P120, P121, P122 P125-P128, P138, P137
P84 -P88
I/O
Shared I/O Ports I/O Ports shared with General Tristate Control GT12 - GT8, used for Input Enable (IE) and Output Enable (OE) Signals. Shared I/O Ports I/O Ports shared with General Clock Control GC12 - GC8, used for Clock (CLK) and Clock Enable (CKE) Signals. Shared I/O Ports I/O Ports shared with Key Control K4 - K0, used for generating Clock (CLK), Clock Enable (CKE), Input Enable (IE) and Output Enable (OE) signals. Shared I/O Ports I/O Ports shared with General Clock Control GC7-GC4 for IQX320 and IQX240B and GC7GC2 for remaining devices, used for Clock (CLK) and Clock Enable (CKE) Signals. Shared I/O Ports I/O Ports shared with General Tristate Control GT7 - GT5 for IQX320 and IQX240B and GT7 - GT4 for remaining devices, used for Input Enable (IE) and Output Enable (OE) Signals. (Dedicated) General Tristate Control Pins Used for Input Enable (IE) and Output Enable (OE) Signals. (Dedicated) General Clock Control Pins Used for Clock (CLK) and Clock Enable (CKE) signals. Shared I/O Ports I/O Ports shared with Column Address (CA) Bus Shared I/O Ports I/O Ports shared with Row Address (RA) Bus Shared I/O Ports I/O Ports shared with P/S, C0 AND C1 Shared I/O Ports RapidConfigure Write Enable (WE) and Write Strobe (STROBE) Hardware Reset Device Reset JTAG Pins For downloading the serial configuration bitstream
P268 - P272
P89 -P93
I/O
P273, P275, P277, P279, P281 P283, P285, P287, P289
P204 - P208
P94 -P98
I/O
P209-P212
P99-P102, P108, P107
I/O
P291, P293, P295
P213 - P215
P131 - P134
P103 - P106
I/O
GT4 - GT0 GC3 - GC0 P296 - P304 CA0 - CA8 P306 - P314 RA0 - RA8 P315 - P317
GT4 - GT0 GC3 - GC0 P216 - P224 CA0 - CA8 P226 - P234 RA0 - RA8 P235 - P237
GT3 - GT0 GC1 - GC0 P140 - P147 CA0 - CA7 P148 - P155 RA0 - RA7 P139, P156, P157 P158, P159 TRST* TDI, TMS, TCK, TDO RCE VDD.PAD1 VDD.PAD2
GT3 - GT0 GC1 - GC0 P110 - P116 CA0 - CA6 P117 - P123 RA0 - RA6 P109, P124, P125 P126, P127 TRST* TDI, TMS, TCK, TDO RCE VDD.PAD1 VDD.PAD2
I I I/O
I/O
I/O
P318, P319 TRST* TDI, TMS, TCK, TDO
P238, P239 TRST* TDI, TMS, TCK, TDO RCE VDD.PAD1 VDD.PAD2 VDD.PAD3 VDD.PAD4
I/O I I I O I P P P P
RCE VDD.PAD1 VDD.PAD2 VDD.PAD3 VDD.PAD4
RapidConfigure Enable Pin For Enabling RapidConfigure interface after reset Power & Ground Pins Power Pins for Group 1 Power Pins for Group 2 Power Pins for Group 3 Power Pins for Group 4 I/O I/O I/O I/O Buffer Buffer Buffer Buffer Drivers. Drivers. Drivers. Drivers.
Table 12. IQX Pin Summary
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IQX Family Data Sheet
IQX320 VDD VDD.X VSS IQX240B VDD VDD.X VSS IQX160 VDD VDD.X VSS IQX128B VDD VDD.X VSS DIR P P P Description Power Pins for on-chip circuitry other than I/O Buffer Drivers. Supply for Switch Matrix. Ground Pins.
Table 12. IQX Pin Summary (Continued)
Supply Voltage IQX320 VDD VDD.PAD1 VDD.PAD2 VDD.PAD3 VDD.PAD4 TDI,TMS,TCK,TRST*, GC0-GC3, GT0-GT4 P000:P079, TDO P080:P159 P160:P239 P240:P319
Pins Powered by Supply Voltage IQX240B TDI,TMS,TCK,TRST*, GC0-GC3, GT0-GT4 P000:P059, TDO P060:P119 P120:P179 P180:P239 IQX160 IQX128B
TDI,TMS,TCK, TDO, TRST*, GC0, TDI,TMS,TCK,TDO,TRST*, GC0, GC1, GT0-GT3 GC1, GT0-GT3 P000:P079 P080:P159 P000:P063 P064:P127
Table 13. Supply Voltage Source
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IQX Family Data Sheet 5.0 ELECTRICAL SPECIFICATIONS
5.1 Absolute Maximum Ratings (1)
Symbol VDD VDD.PAD VIN (2) TJ TSTG IOS Parameter Supply Voltage to Ground Supply Voltage for I/O Buffer Driver Input Voltage Junction Temperature Storage Temperature Current per Port Pin 100 Limits -0.3 to +7.0 -0.3 to +7.0 -0.3 to (VDD.PAD + 0.3) 150 -65 to +150 Units V V V C C mA
Table 14. Absolute Maximum Ratings
5.2 Recommended Operating Conditions
Symbol VDD VDD.PAD (4) TA Parameter Supply Voltage to Ground Supply Voltage for I/O Buffer Driver Operating Temperature Limits 4.75 to 5.25 4.75 to 5.25 2.97 to 3.63 0 to 70 Units V V C
Table 15. Recommended Operating Conditions
5.3 Capacitance (3)
Symbol CIN COUT CPORT CCNTL Parameter Input Capacitance (JTAG pins) Output Capacitance (TDO pin) I/O Signal Port Dedicated General Clock and General Tristate Pin Capacitance Min Max 8 8 10 10 Units pF pF pF pF
Table 16. Capacitance
Notes:
(1) Exposure to absolute maximum rated conditions for extended periods may affect device reliability. (2) A maximum overshoot and undershoot of 2V for a maximum duration of 20 ns is acceptable. (3) Capacitance measured at 25C. Sample-tested only. (4) VDD.PAD1, VDD.PAD2, VDD.PAD3 and VDD.PAD4 can operate at different voltages from each other.
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IQX Family Data Sheet
5.4 DC Electrical Specifications
(TA = 0C to 70C, VDD = 5V5%; V DD .PAD = 5V5%, or V DD .PAD = 3.3V10%)
IQX320, IQX240B Symbol VIH VIL VOH Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage High-Level Output Voltage VOL Low-Level Output Voltage Low-Level Output Voltage |IIH"|" |IIL| IPT |IOZ| IPU-WK IPU-SG IOS Input Leakage Current for I/O ports I/O Port Trickling Current(1) Tristate Output Off-State Current Programmed-Weak Additional Pull-Up Current Programmed-Strong Additional Pull-Up Current Short Circuit Current(1, 2) VDD = Min, VDD.PAD = 4.75V IOH = - 8 mA VDD = Min, VDD.PAD = 2.97V IOH = - 4mA VDD = Min, VDD.PAD = 4.75V IOL = 12 mA VDD = Min, VDD.PAD = 2.97V IOL = 12 mA VDD = Max, 0 VIN VDD.PAD VDD = Max, 0 VIN VDD = Max, 0 VIN VDD.PAD VDD.PAD Conditions Min 2.0 -0.3 2.4 2.4 2.5 9 -60 Max VDD + 0.3 0.8 0.4 0.4 5 -25 5 4.0 13.5 85 8 80 0.2 IQX160, IQX128B Min 2.0 -0.3 2.4 2.4 2.0 8.0 -60 Max VDD + 0.3 0.8 0.4 0.4 5 -25 5 4.0 13.5 85 8 80 0.1 Unit
V V V V V V A A A mA mA mA mA mA A mA/ MHz
VDD = VDD.PAD = 4.75V, VO = GND VDD = VDD.PAD = 4.75V, VO = GND VDD = Max, VO = GND VDD = Max, I/O = GND, CP = On VDD = Max, I/O = GND, CP = Off VDD.PAD = 5.25V, All I/O = NC VDD = Max, VO = GND VDD.PAD = 5.25V, VDD = Max, No Load, @ 1.0 MHZ clock input, connect one output per input VDD.PAD = 5.25V, VDD = Max, No Load, @ 1.0 MHZ clock input, connect one output per input
IDDQ_CORE Quiescent Core Power Supply Current IDDQ_PAD Quiescent Pad Power Supply Current
QDDD_CORE Dynamic CorePower Supply Current
QDDD_PAD Dynamic Pad Power Supply Current
-
0.1
-
0.05
mA/ MHz
Table 17. DC Electrical Specifications
Notes:
(1) These parameters are guaranteed but not tested in production. (2) No more than one output should be tested at a time and the duration of the test should be limited to less than one second.
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IQX Family Data Sheet
5.5 AC Electrical Specifications for IQX320 and IQX240B
(TA = 0C to 70C, VDD = 5V5%; V DD.PAD = 5V5%, or V DD.PAD = 3.3V10%. Assume two I/O ports connected through the Switch Matrix with 35 pF external loading)
Speed Grade Symbol fRIO tW-RIO tS-RIO tH-RIO tCO-RIO fRI tW-RI tS-RI tH-RI tCO-RI fRO tW-RO tS-RO tH-RO tCO-RO tPHL, tPLH tSK tW+ tWRDATA tPZH-IT, tPZL-IT tPZH-OT, tPZL-OT tPHZ-OT, tPLZ-OT tW-LI tS-LI tH-LI tCO-LI tP-LIT tW-LO tS-LO tH-LO tCO-LO tP-LOT tKW-RI tKS-RI tKH-RI tKCO-RI Parameter Register Input/Output, Clock Frequency(1, 2) Register Input/Output, Clock Pulse Width, Low or High(1, 2) Register Input/Output, Data Setup Time to CLK Register Input/Output, CLK to Data Hold Time Register Input/Output, Clock to Output Data Valid Register Input, Clock Frequency (1) Register Input, Clock Pulse Width, Low or High Register Input, Data Setup Time to CLK Register Input, CLK to Data Hold Time Register Input, Clock to Output Data Valid Register Output, Clock Pulse Frequency(1) Register Output, Clock Width, Low or High Register Output, Data Setup Time to CLK Register Output, CLK to Data Hold Time Register Output, Clock to Output Data Valid One Way Signal Propagation Delay Skew Between Output Ports(1) Input Flow Through Positive Pulse Width(2) Input Flow Through Negative Pulse Width(2) NRZ Data Rate(1, 2) Input Enable (GT) to Data Valid Output Enable (GT) to Data Valid Output Enable (GT) to Output at High Z(1) Latch Input, Latch Enable (GC) Pulse Width, Low or High Latch Input, Data Setup Time to Latch Enable (GC) Trailing Edge Latch Input, Data to Latch Enable (GC) Trailing Edge Hold Time Latch Input, Latch Enable (GC) Leading Edge to Data Out Delay Latch Input, Transparent Mode Propagation Delay Latch Output, Latch Enable (GC) Pulse Width, Low or High Latch Output, Data Setup Time to Latch Enable (GC) Trailing Edge Latch Output, Data to Latch Enable (GC) Trailing Edge Hold Time Latch Output, Latch Enable (GC) Leading Edge to Data Out Delay Latch Output, Transparent Mode Propagation Delay Register Input, Minimum Pulse Width of KEY as Clock Enable, Low or High Register Input, Clock Enable (Key) Setup Time to CLK (GC) Register Input, CLK (GC) to Clock Enable (Key) Hold Time Register Input, Key Clock to Output Data Valid 6.0 3.0 2.0 13.0 3.5 2.0 15.5 4.5 4.5 0.0 25.0 10.0 4.5 2.5 2.0 15.0 10.0 5.5 5.0 0.0 27.5 12.5 7.0 4.5 6.5 180 12.0 12.0 8.5 5.5 3.0 2.0 17.5 12.5 4.5 4.5 0.0 9.5 10.0 1.5 6.0 8.0 150 13.0 13.0 10.5 4.5 2.5 2.0 12.5 100 5.5 5.0 0.0 11.5 12.5 1.5 4.5 2.5 2.0 9.5 80 5.5 3.0 2.0 15.0 80 -10 -12 Ref. Min Max Min Max Units Figure 100 5.5 3.0 2.0 11.5 66 80 MHz ns ns ns ns MHz ns ns ns ns MHz ns ns ns ns ns ns ns ns Mb/s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 21 20 19 17 18 16 15 14 13
Table 18. AC Electrical Specifications for IQX320 and IQX240B
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IQX Family Data Sheet
Speed Grade Symbol tKW-RO tKS-RO tKH-RO tKCO-RO tKPZH-IT tKPZL-IT Parameter Register Output, Minimum Pulse Width of KEY as Clock Enable, Low or High Register Output, Clock Enable (Key) Setup Time to CLK (GC) Register Output, CLK (GC) to Clock Enable (Key) Hold Time Register Output, Key Clock to Output Data Valid Input Enable (Key) to Data Valid -10 -12 Ref. Min Max Min Max Units Figure 6.0 5.0 0.0 7.5 11.0 9.0 9.0 6.0 3.0 2.0 13.0 10.0 6.0 5.0 0.0 7.5 10.0 66 6.0 2.5 0.0 2.5 0.0 9.5 11.5 11.5 10.5 30.0 6.0 0.0 3.0 35.0 10 20.0 4.0 0.0 15.0 20.0 4.0 0.0 15.0 32.5 7.0 0.0 3.0 37.5 10 7.0 3.5 0.0 3.5 0.0 11.5 14.0 13.5 12.5 7.0 5.5 0.0 9.5 12.5 50 7.0 3.5 2.0 15.5 12.5 7.0 5.5 0.0 9.5 13.5 11.0 11.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns ns ns ns 29 28 27 26 25 23 24 22
tKPZH-OT tKPZL-OT Output Enable (Key) to Data Valid tKPHZ-OT tKPLZ-OT Output Enable (Key) to Output at High Z(1) tKW-LI tKS-LI tKH-LI tKCO-LI tKP-LIT tKW-LO tKS-LO tKH-LO tKCO-LO tKP-LOT fKCNT tWKCNT tS_KCKE tH_KCKE tS_KRST tH_KRST tKCLK_OE tKCLK_IE tP_KCLR tP_KF1F TRC tW+ -RC , tW- -RC tS-RC tH-RC tP-RC fJTAG tW-JTAG tS-JTAG tH-JTAG tP-JTAG Latch Input, Minimum Pulse Width of KEY as Latch Enable, Low or High Latch Input, Data Setup Time to Latch Enable (Key) Trailing Edge Latch Input, Data to Latch Enable (Key) Trailing Edge Hold Time Latch Input, Latch Enable (Key) Leading Edge to Data Out Latch Input, Transparent Mode Propagation Delay Latch Output, Minimum Pulse Width of KEY as Latch Enable, Low or High Latch Output, Data Setup Time to Latch Enable (Key) Trailing Edge Latch Output, Data to Latch Enable (Key) Trailing Edge Hold Time Latch Output, Latch Enable (Key) Leading Edge to Data Out Latch Output, Transparent Mode Propagation Delay Key Counter, Input Clock Frequency Key Counter Clock, Pulse Width Key Counter, Enable Setup Time to KCLK Key Counter, KCLK to Enable Hold Time Key Counter, Reset Setup Time to KCLK Key Counter, KCLK to Reset Hold Time Key Counter, Clock to Output Data Valid or Output High Z Key Counter, Clock to Input Data Valid Key Counter, Clear to Output Active / High Z Delay Key Counter, Force 0x1F to Output Active / High Z Delay RapidConfigure Strobe Period RapidConfigure Strobe Pulse Width RapidConfigure Address and Data Setup Time to Strobe RapidConfigure Address and Data Hold Time to Strobe RapidConfigure Strobe Falling Edge to Data Valid (Make Connection) JTAG Clock (TCK) Frequency JTAG Clock (TCK) Pulse Width JTAG Setup Time JTAG Hold Time JTAG Clock to Output Data Valid
Table 18. AC Electrical Specifications for IQX320 and IQX240B (Continued)
Notes:
(1) These parameters are guaranteed but not tested in production. (2) The timing parameters are specified for a configuration where an Input Port is driving one Output Port. For configurations where an Input Port is driving two or more Output Ports, the timing parameters are de-rated as shown in Section 5.7 or Table 20. These parameters are guaranteed but not tested in production.
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IQX Family Data Sheet
5.6 AC Electrical Specifications for IQX160 and IQX128B
(TA = 0C to 70C, VDD = 5V5%; V DD .PAD = 5V5%, or V DD .PAD = 3.3V10%. Assume two I/O Ports connected through the Switch Matrix with 35 pF external loading.)
Speed Grade Symbol fRIO tW-RIO tS-RIO tH-RIO tCO-RIO fRI tW-RI tS-RI tH-RI tCO-RI fRO tW-RO tS-RO tH-RO tCO-RO tPHL, tPLH tBR tSK tW+ tWRDATA tPZH-IT, tPZL-IT tPZH-OT, tPZL-OT tPHZ-OT, tPLZ-OT tW-LI tS-LI tH-LI tCO-LI tP-LIT tW-LO tS-LO tH-LO tCO-LO tP-LOT tKW-RI tKS-RI tKH-RI tKCO-RI Parameter Register Input/Output, Clock Frequency(1, 2) Register Input/Output, Clock Pulse Width, Low or High(1, 2) Register Input/Output, Data Setup Time to CLK Register Input/Output, CLK to Data Hold Time Register Input/Output, Clock to Output Data Valid Register Input, Clock Frequency(1) Register Input, Clock Pulse Width, Low or High Register Input, Data Setup Time to CLK Register Input, CLK to Data Hold Time Register Input, Clock to Output Data Valid Register Output, Clock Pulse Frequency (1) Register Output, Clock Width, Low or High Register Output, Data Setup Time to CLK Register Output, CLK to Data Hold Time Register Output, Clock to Output Data Valid One Way Signal Propagation Delay Additional Delay in Bus Repeater (BR) Mode (1, 2) Skew Between Output Ports(1) Input Flow Through Positive Pulse Width(2) Input Flow Through Negative Pulse Width(2) NRZ Data Rate (1, 2) Input Enable (GT) to Data Valid Output Enable (GT) to Data Valid Output Enable (GT) to Output at High Z (1) Latch Input, Latch Enable (GC) Pulse Width, Low or High Latch Input, Data Setup Time to Latch Enable (GC) Trailing Edge Latch Input, Data to Latch Enable (GC) Trailing Edge Hold Time Latch Input, Latch Enable (GC) Leading Edge to Data Out Delay Latch Input, Transparent Mode Propagation Delay Latch Output, Latch Enable (GC) Pulse Width, Low or High Latch Output, Data Setup Time to Latch Enable (GC) Trailing Edge Latch Output, Data to Latch Enable (GC) Trailing Edge Hold Time Latch Output, Latch Enable (GC) Leading Edge to Data Out Delay Latch Output, Transparent Mode Propagation Delay Register Input, Minimum Pulse Width of KEY as Clock Enable, Low or High Register Input, Clock Enable (Key) Setup Time to CLK (GC) Register Input, CLK (GC) to Clock Enable (Key) Hold Time Register Input, Key Clock to Output Data Valid 5.0 2.5 2.0 10.5 3.3 4.0 0.0 35.0 8.0 6.0 3.0 2.0 13.0 3.3 2.0 4.0 12.0 9.0 4.5 5.0 0.0 40.0 10.0 3.5 4.5 200 10.0 9.0 7.0 4.5 3.0 4.0 15.0 10.0 3.3 3.0 0.0 8.5 7.5 0.0 1.5 4.5 5.0 180 12.5 10.0 8.5 3.3 2.0 0.0 12.0 133 4.5 4.0 0.0 10.0 10.0 0.0 1.5 3.3 2.0 0.0 8.5 100 4.5 3.0 0.0 15.0 100 Min -7 Max 133 4.5 3.0 0.0 10.0 80 -10 Min Ref. Max Units Figure 100 MHz ns ns ns ns MHz ns ns ns ns MHz ns ns ns ns ns ns ns ns ns Mb/s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 21 20 19 18 17 16 15 14 13
Table 19. AC Electrical Specifications for IQX160 and IQX128B
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IQX Family Data Sheet
Speed Grade Symbol tKW-RO tKS-RO tKH-RO tKCO-RO tKPZH-IT tKPZL-IT tKPZH-OT tKPZL-OT tKPHZ-OT tKPLZ-OT tKW-LI tKS-LI tKH-LI tKCO-LI tKP-LIT tKW-LO tKS-LO tKH-LO tKCO-LO tKP-LOT fKCNT tWKCNT tS_KCKE tH_KCKE tS_KRST tH_KRST tKCLK_OE tKCLK_IE tP_KCLR tP_KF1F TRC tW+ -RC, tW- -RC tS-RC tH-RC tP-RC fJTAG tW-JTAG tS-JTAG tH-JTAG tP-JTAG Parameter Register Output, Minimum Pulse Width of KEY as Clock Enable, Low or High Register Output, Clock Enable (Key) Setup Time to CLK (GC) Register Output, CLK (GC) to Clock Enable (Key) Hold Time Register Output, Key Clock to Output Data Valid Input Enable (Key) to Data Valid Output Enable (Key) to Data Valid Output Enable (Key) to Output at High Z(1) Latch Input, Minimum Pulse Width of KEY as Latch Enable, Low or High Latch Input, Data Setup Time to Latch Enable (Key) Trailing Edge Latch Input, Data to Latch Enable (Key) Trailing Edge Hold Time Latch Input, Latch Enable (Key) Leading Edge to Data Out Latch Input, Transparent Mode Propagation Delay Latch Output, Minimum Pulse Width of KEY as Latch Enable, Low or High Latch Output, Data Setup Time to Latch Enable (Key) Trailing Edge Latch Output, Data to Latch Enable (Key) Trailing Edge Hold Time Latch Output, Latch Enable (Key) Leading Edge to Data Out Latch Output, Transparent Mode Propagation Delay Key Counter, Input Clock Frequency Key Counter Clock, Pulse Width Key Counter, Enable Setup Time to KCLK Key Counter, KCLK to Enable Hold Time Key Counter, Reset Setup Time to KCLK Key Counter, KCLK to Reset Hold Time Key Counter, Clock to Output Data Valid or Output High Z Key Counter, Clock to Input Data Valid Key Counter, Clear to Output Active / High Z Delay Key Counter, Force 0x1F to Output Active / High Z Delay RapidConfigure Strobe Period RapidConfigure Strobe Pulse Width RapidConfigure Address and Data Setup Time to Strobe RapidConfigure Address and Data Hold Time to Strobe RapidConfigure Strobe Falling Edge to Data Valid (Make Connection) JTAG Clock (TCK) Frequency JTAG Clock (TCK) Pulse Width JTAG Setup Time JTAG Hold Time JTAG Clock to Output Data Valid 20.0 4.0 0.0 15.0 15.0 6.0 2.0 0.0 25.0 10 20.0 4.0 0.0 15.0 5.0 2.0 0.0 2.0 0.0 8.0 9.5 9.5 8.5 17.0 7.5 3.0 0.0 30.0 10 5.0 4.5 0.0 6.5 7.5 80 6.0 2.5 0.0 2.5 0.0 9.5 11.5 11.5 10.5 5.0 2.5 2.0 10.5 7.5 6.0 5.0 0.0 7.5 10.0 66 Min 5.0 4.5 0.0 6.5 9.0 7.5 7.5 6.0 3.0 2.0 13.0 10.0 -7 Max 6.0 5.0 0.0 7.5 11.0 9.0 9.0 -10 Min Ref. Max Units Figure ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns ns ns ns 29 28 27 26 25 24 23 22
Table 19. AC Electrical Specifications for IQX160 and IQX128B (Continued)
Notes:
(1) These parameters are guaranteed but not tested in production. (2) The timing parameters are specified for a configuration where an Input Port is driving one Output Port. For configurations where an Input Port is driving two or more Output Ports, the timing parameters are de-rated as shown in Section 5.7 or Table 20. These parameters are guaranteed but not tested in production.
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Revision 5.0
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IQX Family Data Sheet
5.7 Parameter De-rating For One-to-Many Connections
IQX320 Symbol CNMAX tPD tW f Parameter Maximum Number of Connections Per Input Increase in tPD for Every Additional Output Port Connected to an Input Port Increase in tw+ and tw- for Every Additional Output Port Connected to an Input Port Decrease in Maximum Operating Frequency Every Additional Output Port Connected to an Input Port 32 0.35 200 1 IQX240B 32 0.35 200 1 IQX160 32 0.25 160 0.75 IQX128B Units ns ps MHz 32 0.25 160 0.75 Min Max Min Max Min Max Min Max
Table 20. Parameter De-rating For One-to-Many Connections
June 2000
Revision 5.0
35
IQX Family Data Sheet
5.8 Test Circuit and Timing Diagrams
tF
VDD.Pad 500 Pulse Generator Vin D.U.T. Vout 500 35pF* 90% 7.0V
Parameter Switch Tested Position tPLZ/tPZL Closed All Others Open
tR
3.0V 1.5V 0V
Negative Pulse 10%
tW
90% Positive Pulse 10% 3.0V 1.5V 0V
50
tF = 3 ns (max) tR = 3 ns (max)
* Load capacitance includes jig and probe capacitance.
tR
tF
Figure 12. Test Circuit and Waveform Definition
tW-RIO GC (CLK) tS-RIO tH-RIO RI
InPort D Q
tW-RIO
Switch Matrix
RO
D Q
Out Port
InPort
Dn
Dn+1
OutPort
CE CLK CE
Dn-2 tCO-RIO
Dn-1
Dn
Figure 13. Registered Input and Registered Output Mode Timing (ICLK, OCLK Synchronized)
tW-RI GC (CLK) tS-RI tH-RI RI
InPort CLK CE D Q
tW-RI
Switch Matrix
OP
OutPort
InPort OutPort
Dn Dn-1 tCO-RI
Dn+1 Dn Dn+1
Figure 14. Registered Input Mode Timing
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Revision 5.0
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IQX Family Data Sheet
tW-RO GC (CLK) tS-RO tH-RO IN
InPort CLK CE
tW-RO
RO
Switch Matrix
D Q Out Port
InPort OutPort
Dn Dn-1 tCO-RO
Dn+1 Dn Dn+1
Figure 15. Registered Output Mode Timing
InPort 1 InPort 2
tW+ tPLH tPHL
1.5V
IN
InPort 1
OP
OutPort 1
OutPort 1 tSK
OutPort 2
Switch Matrix
InPort 2
tSK
OutPort 2
Figure 16. I/O Port Timing (Flow-through Mode)
GT (IE)
InPort IN OP
OutPort
tPZH-IT tPZL-IT
IE InPort
Switch Matrix
OutPort
Figure 17. Input Enable Timing (Flow-through Mode)
June 2000
Revision 5.0
37
IQX Family Data Sheet
GT (OE)
InPort IN
InPort OE
tPZH-OT tPZL-OT tPLZ-OT
VOL VOL +0.3V
tPHZ-OT
VOH VOH - 0.3V
Switch Matrix
OP
OutPort
OutPort
Figure 18. Output Enable Timing (Flow-through Mode)
tH-LI tS-LI GC (CLK) tW-LI InPort
LI
InPort D LE Q
Switch Matrix
OP
OutPort
tP-LIT OutPort tCO-LI
Figure 19. Latched Input Mode Timing
CLK
tH-LO tS-LO GC (CLK) tW-LO InPort
IN
InPort CLK
LO Switch Matrix
D LE Q OutPort
tP-LOT OutPort tCO-LO
Figure 20. Latched Output Mode Timing
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Revision 5.0
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IQX Family Data Sheet
GC (CLK)
tKH-RI tKS-RI
KEY (CKE )
Valid tKW-RI
RI
InPort CLK CKE CE D Q
Switch Matrix
OP
OutPort
InPort
tKCO-RI
OutPort
Figure 21. Key Timing for Register Input, Clock Enable (CKE)
GC (CLK)
tKH-RO tKS-RO
KEY (CKE)
Valid tKW-RO
IN
InPort CLK CKE
Switch Matrix
RO
D Q OutPort
InPort
tKCO-RO
OutPort
CE
Figure 22. Key Timing for Register Output, Clock Enable (CKE)
Key (IE)
Valid
Valid
InPort IN OP
OutPort
tKPZH-IT tKPZL-IT
IE InPort
Switch Matrix
OutPort
Figure 23. Key Timing for Input Enable
June 2000
Revision 5.0
39
IQX Family Data Sheet
Key (OE)
Valid
Valid
InPort IN
InPort OE
tKPZH-OT tKPZL-OT tKPLZ-OT
VOL VOL +0.3V
tKPHZ-OT
VOH VOH - 0.3V
Switch Matrix
OP
OutPort
OutPort
Figure 24. Key Timing for Output Enable
GC (CLK)
KEY (CKE)
Valid tKH-LI tKS-LI
InPort LI
InPort CKE LE CLK D Q
Switch OP Matrix OutPort OutPort
tKP-LIT
tKCO-LI
Figure 25. Key Timing for Latch Input, Enable (CKE)
GC (CLK)
KEY (CKE)
Valid tKH-LO tKS-LO
InPort IN
InPort CKE LE CLK
Switch Matrix
LO
D Q OutPort
tKP-LOT
OutPort
tKCO-LO
Figure 26. Key Timing for Latch Output, Enable (CKE)
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Revision 5.0
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IQX Family Data Sheet
K0/KCLK K1/KCKE a b c d e tH_KCKE f g h j m n p r t
tS_KCKE
tS_KRST K2/KRST tH_KRST K3/KCLR K4/K1F
Key Bus (Internal)
0
TG1*
TG2*
TG1*
0
1
0
1
2
1F
IN
InPort1 OE
Switch Matrix
OP
OutPort1
tKCLK_OE tKCLK_OE tKCLK_OE
VOL VOL + 0.3V
tKCLK_OE
VOH VOH - 0.3V
OutPort1
IE InPort2
IN
Switch Matrix
OP
OutPort2
InPort2 tKCLK_IE OutPort2
* TG1 and TG2 are the 5-bit tag values programmed in the I/O Ports OutPort1 and InPort2 respectively.
tKCLK_IE
Figure 27. Key Counter Timing
TRC
STROBE
tW+RC
tW-RC
tH-RC tS-RC
RA[7:0] CA[3:0]
tS-RC
P/S, C1, C0
tS-RC
tH-RC
tS-RC
WE
tH-RC
tP-RC
Output Port
Make Connection
Break Connection
Figure 28. RapidConfigure Timing June 2000 Revision 5.0 41
IQX Family Data Sheet
tW-JTAG TCK
tW-JTAG
tS-JTAG tH-JTAG TDI, TMS tP-JTAG TDO
Figure 29. JTAG Timing
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Revision 5.0
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IQX Family Data Sheet 6.0 PINOUT
6.1 IQX320 [PBGA/416L] Package Pinout by Name
Name Pin# GC0 E2 GC1 D1 GC2 E3 GC3 C3 GT0 D22 GT1 E24 GT2 AB5 GT3 AA5 GT4 D2 P000 D5 P001 E14 P002 E6 P003 E11 P004 D6 P005 E9 P006 E8 P007 C6 P008 E7 P009 B6 P010 D7 P011 C7 P012 E10 P013 B7 P014 D9 P015 A7 P016 D8 P017 C8 P018 D10 P019 B8 P020 C10 P021 C9 P022 D11 P023 B9 P024 C11 P025 A9 P026 E12 P027 B10 P028 D12 P029 B11 P030 C12 P031 B12 P032 E13 P033 A13 P034 D13 P035 B14 P036 C14 P037 A15 P038 D14 P039 B16 P040 C15 P041 B17 P042 D15 Name P043 P044 P045 P046 P047 P048 P049 P050 P051 P052 P053 P054 P055 P056 P057 P058 P059 P060 P061 P062 P063 P064 P065 P066 P067 P068 P069 P070 P071 P072 P073 P074 P075 P076 P077 P078 P079 P080 P081 P082 P083 P084 P085 P086 P087 P088 P089 P090 P091 P092 P093 P094 Pin# A18 E15 B18 C16 C18 D16 B19 E16 C19 C17 B20 D17 C20 E17 A21 D18 B21 D19 C21 E18 B22 E19 C22 D20 B23 E20 A24 D21 C23 E21 B24 E22 C25 C24 D25 E23 C26 F24 D26 G23 E25 G24 D27 H23 E26 H24 F25 J23 F26 J24 G25 K23 Name P095 P096 P097 P098 P099 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P145 P146 Pin# G26 K24 G27 K25 H25 L23 H26 L24 J25 L25 J26 M25 J27 M23 K26 M24 L26 N23 M26 N24 N27 P25 N26 P23 R26 P24 R27 R25 T26 R24 U26 R23 V27 T25 V26 T24 V25 T23 W26 U25 W25 U24 X26 V24 X25 W24 Y27 V23 Y26 Y24 Y25 X23 Name P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P158 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 P178 P179 P180 P181 P182 P183 P184 P185 P186 P187 P188 P189 P190 P191 P192 P193 P194 P195 P196 P197 P198 Pin# AA26 W23 AA25 Y23 AC27 U23 AB25 AA24 AC26 AA23 AD25 AB23 AC25 AB22 AD24 AC23 AE25 AB21 AE24 AC22 AD23 AC21 AF24 AB20 AE23 AC20 AD22 AB19 AE22 AC19 AD21 AB18 AE21 AC18 AF21 AD18 AD20 AB17 AE20 AC17 AD19 AD17 AE19 AB16 AF19 AC16 AE18 AD16 AE17 AC15 AE16 AB15 Name P199 P200 P201 P202 P203 P204 P205 P206 P207 P208 P209 P210 P211 P212 P213 P214 P215 P216 P217 P218 P219 P220 P221 P222 P223 P224 P225 P226 P227 P228 P229 P230 P231 P232 P233 P234 P235 P236 P237 P238 P239 P240 P241 P242 P243 P244 P245 P246 P247 P248 P249 P250 Pin# AF15 AD14 AE15 AB14 AE14 AC14 AE13 AD13 AE12 AC13 AE11 AB13 AF10 AC12 AE10 AB12 AD10 AC11 AE9 AC10 AD9 AC9 AE8 AB11 AD8 AC8 AF7 AB10 AE7 AB8 AD7 AB9 AE6 AB7 AD6 AC7 AE5 AC6 AF4 AB6 AD5 AC5 AE4 AD3 AD4 AB4 AC3 AA4 AD2 Y5 AC2 Y4 Name P251 P252 P253 P254 P255 P256 P257 P258 P259 P260/GT12 P261/GT11 P262 P263/GT10 P264 P265/GT9 P266 P267/GT8 P268/GC12 P269/GC11 P270/GC10 P271/GC9 P272/GC8 P273/K4 P274 P275/K3 P276 P277/K2 P278 P279/K1 P280 P281/K0 P282 P283/GC7 P284 P285/GC6 P286 P287/GC5 P288 P289/GC4 P290 P291GT7 P292 P293/GT6 P294 P295/GT5 P296/CA0 P297/CA1 P298/CA2 P299/CA3 P300/CA4 P301/CA5 P302/CA6 Pin# AB3 X5 AC1 X4 AB2 W5 AA3 W4 AA2 V5 Y3 V4 Y2 V3 Y1 U5 X3 U4 X2 U3 W3 T5 W1 T4 V2 T3 U2 R4 T2 R5 R1 P3 P2 P4 N1 N3 M2 P5 L2 N4 K1 M3 K2 L3 K3 N5 J2 M5 J3 M4 H2 L4 Name P303/CA7 P304/CA8 P305 P306/RA0 P307/RA1 P308/RA2 P309/RA3 P310/RA4 P311/RA5 P312/RA6 P313/RA7 P314/RA8 P315/P/S P316/C0 P317/C1 P318/WE P319/STROBE RCE TCK TDI TDO TMS TRST* VDD VDD VDD VDD VDD.PAD1 VDD.PAD1 VDD.PAD1 VDD.PAD1 VDD.PAD1 VDD.PAD1 VDD.PAD1 VDD.PAD1 VDD.PAD2 VDD.PAD2 VDD.PAD2 VDD.PAD2 VDD.PAD2 VDD.PAD2 VDD.PAD2 VDD.PAD2 VDD.PAD2 VDD.PAD3 VDD.PAD3 VDD.PAD3 VDD.PAD3 VDD.PAD3 VDD.PAD3 VDD.PAD3 VDD.PAD3 Pin# H3 L5 G1 K4 G2 K5 G3 J4 F2 J5 H5 G4 G5 F4 F5 E5 D3 C4 A4 B3 C5 B4 B5 A19 H27 W2 AD12 A5 A8 A10 A14 A23 B13 B15 C13 E27 F23 K27 N25 P26 P27 W27 X24 AB27 AD11 AD15 AF5 AF9 AF13 AF14 AF18 AF20 Name VDD.PAD3 VDD.PAD4 VDD.PAD4 VDD.PAD4 VDD.PAD4 VDD.PAD4 VDD.PAD4 VDD.PAD4 VDD.PAD4 VDD.PAD4 VDD.PAD4 VDD.X VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin# AF23 E1 H4 J1 N2 P1 R2 R3 V1 X1 AB1 F3 A6 A11 A12 A16 A17 A20 A22 AA1 AA27 AB24 AB26 AC4 AC24 AD26 AE3 AF6 AF8 AF11 AF12 AF16 AF17 AF22 B25 C2 D4 D23 D24 E4 F1 F27 H1 L1 L27 M1 M27 T1 T27 U1 U27 X27
Table 21. IQX320 [PBGA/416L] Package Pinout by Name
June 2000
Revision 5.0
43
IQX Family Data Sheet
6.2 IQX320 [PBGA/416L] Package Pinout by Location
Pin# A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 C2 C3 C4 C5 C6 C7 C8 C9 C10 Name TCK VDD.PAD1 VSS P015 VDD.PAD1 P025 VDD.PAD1 VSS VSS P033 VDD.PAD1 P037 VSS VSS P043 VDD VSS P057 VSS VDD.PAD1 P069 TDI TMS TRST* P009 P013 P019 P023 P027 P029 P031 VDD.PAD1 P035 VDD.PAD1 P039 P041 P045 P049 P053 P059 P063 P067 P073 VSS VSS GC3 RCE TDO P007 P011 P017 P021 P020 Pin# Name Pin# Name Pin# C11 P024 E11 P003 J24 C12 P030 E12 P026 J25 C13 VDD.PAD1 E13 P032 J26 C14 P036 E14 P001 J27 C15 P040 E15 P044 K1 C16 P046 E16 P050 K2 C17 P052 E17 P056 K3 C18 P047 E18 P062 K4 C19 P051 E19 P064 K5 C20 P055 E20 P068 K23 C21 P061 E21 P072 K24 C22 P065 E22 P074 K25 C23 P071 E23 P078 K26 C24 P076 E24 GT1 K27 C25 P075 E25 P083 L1 C26 P079 E26 P087 L2 D1 GC1 E27 VDD.PAD2 L3 L4 D2 GT4 F1 VSS D3 P319/STROBE F2 P311/RA5 L5 D4 VSS F3 VDD.X L23 D5 P000 F4 P316/C0 L24 D6 P004 F5 P317/C1 L25 D7 P010 F23 VDD.PAD2 L26 D8 P016 F24 P080 L27 D9 P014 F25 P089 M1 D10 P018 F26 P091 M2 M3 D11 P022 F27 VSS D12 P028 G1 P305 M4 D13 P034 G2 P307/RA1 M5 D14 P038 G3 P309/RA3 M23 D15 P042 G4 P314/RA8 M24 D16 P048 G5 P315/P/S M25 D17 P054 G23 P082 M26 D18 P058 G24 P084 M27 D19 P060 G25 P093 N1 D20 P066 G26 P095 N2 D21 P070 G27 P097 N3 D22 GT0 H1 VSS N4 D23 VSS H2 P301/CA5 N5 H3 P303/CA7 N23 D24 VSS D25 P077 H4 VDD.PAD4 N24 D26 P081 H5 P313/RA7 N25 D27 P085 H23 P086 N26 E1 VDD.PAD4 H24 P088 N27 E2 GC0 H25 P099 P1 E3 GC2 H26 P101 P2 H27 VDD P3 E4 VSS J1 VDD.PAD4 P4 E5 P318/WE E6 P002 J2 P297/CA1 P5 E7 P008 J3 P299/CA3 P23 E8 P006 J4 P310/RA4 P24 E9 P005 J5 P312/RA6 P25 E10 P012 J23 P090 P26 Name P092 P103 P105 P107 P291/GT7 P293/GT6 P295/GT5 P306/RA0 P308/RA2 P094 P096 P098 P109 VDD.PAD2 VSS P289/GC4 P294 P302/CA6 P304/CA8 P100 P102 P104 P111 VSS VSS P287/GC5 P292 P300/CA4 P298/CA2 P108 P110 P106 P113 VSS P285/GC6 VDD.PAD4 P286 P290 P296/CA0 P112 P114 VDD.PAD2 P117 P115 VDD.PAD4 P283/GC7 P282 P284 P288 P118 P120 P116 VDD.PAD2 Pin# P27 R1 R2 R3 R4 R5 R23 R24 R25 R26 R27 T1 T2 T3 T4 T5 T23 T24 T25 T26 T27 U1 U2 U3 U4 U5 U23 U24 U25 U26 U27 V1 V2 V3 V4 V5 V23 V24 V25 V26 V27 W1 W2 W3 W4 W5 W23 W24 W25 W26 W27 X1 X2 Name VDD.PAD2 P281/K0 VDD.PAD4 VDD.PAD4 P278 P280 P126 P124 P122 P119 P121 VSS P279/K1 P276 P274 P272/GC8 P132 P130 P128 P123 VSS VSS P277/K2 P270/GC10 P268/GC12 P266 P152 P136 P134 P125 VSS VDD.PAD4 P275/K3 P264 P262 P260/GT12 P142 P138 P131 P129 P127 P273/K4 VDD P271/GC9 P258 P256 P148 P140 P135 P133 VDD.PAD2 VDD.PAD4 P269/GC11 Pin# X3 X4 X5 X23 X24 X25 X26 X27 Y1 Y2 Y3 Y4 Y5 Y23 Y24 Y25 Y26 Y27 AA1 AA2 AA3 AA4 AA5 AA23 AA24 AA25 AA26 AA27 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 Name P267/GT8 P254 P252 P146 VDD.PAD2 P139 P137 VSS P265/GT9 P263/GT10 P261/GT11 P250 P248 P150 P144 P145 P143 P141 VSS P259 P257 P246 GT3 P156 P154 P149 P147 VSS VDD.PAD4 P255 P251 P244 GT2 P238 P232 P228 P230 P226 P222 P214 P210 P202 P198 P190 P184 P178 P174 P170 P164 P160 P158 VSS P153 Pin# Name AB26 VSS AB27 VDD.PAD2 AC1 P253 AC2 P249 AC3 P245 AC4 VSS AC5 P240 AC6 P236 AC7 P234 AC8 P224 AC9 P220 AC10 P218 AC11 P216 AC12 P212 AC13 P208 AC14 P204 AC15 P196 AC16 P192 AC17 P186 AC18 P180 AC19 P176 AC20 P172 AC21 P168 AC22 P166 AC23 P162 AC24 VSS AC25 P159 AC26 P155 AC27 P151 AD2 P247 AD3 P242 AD4 P243 AD5 P239 AD6 P233 AD7 P229 AD8 P223 AD9 P219 AD10 P215 AD11 VDD.PAD3 AD12 VDD AD13 P206 AD14 P200 AD15 VDD.PAD3 AD16 P194 AD17 P188 AD18 P182 AD19 P187 AD20 P183 AD21 P177 AD22 P173 AD23 P167 AD24 P161 AD25 P157 Pin# AD26 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 Name VSS VSS P241 P235 P231 P227 P221 P217 P213 P209 P207 P205 P203 P201 P197 P195 P193 P189 P185 P179 P175 P171 P165 P163 P237 VDD.PAD3 VSS P225 VSS VDD.PAD3 P211 VSS VSS VDD.PAD3 VDD.PAD3 P199 VSS VSS VDD.PAD3 P191 VDD.PAD3 P181 VSS VDD.PAD3 P169
Table 22. IQX320 [PBGA/416L] Package Pinout by Location
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Revision 5.0
June 2000
IQX Family Data Sheet
6.3 IQX320 [PBGA/416L] Package Footprint
AF AE AD AC AB AA 1 2 3 4 Y X W V U T R P N M L K J H G F E D C B A 1 2
P253 VDD4 VSS P265 / P247 P249 P255 P259 P263 / VSS P242 P245 P251 P257 P261 / P237 P241 P243 VSS P244 P246 P250 VDD4 P273/ VDD4 VSS VSS P281/ VDD4 P285/ VSS VSS P291/ VDD4 VSS P305 VSS P311/ VDD4 GC1 GC0 GT4 VSS
5 VDD3 P235 P239 P240 GT2 6 VSS
P231 P233 P236 P238
P269/ VDD P275/ P277 / P267/ P271/ P264 P270 / P254 P258 P262 P268 / GT3 P248 P252 P256 P260/ P266
P279 VDD4 P283/ VDD4 P287 P289 P293/ P297/ P301/ P307 / / / / P276 VDD4 P282 P286 P292 P294 P295/ P299/ P303/ P309 / P274 P278 P284 P290 P300 P302 P306/ P310/ VDD4 P314 / / / P272 P280 P288 P296/ P298 P304 P308/ P312/ P313/ P315 / / / /
VDD.X GC2 P316/ P317/ VSS
P319 GC3 TDI 3 / VSS RCE TMS TCK 4
P318/ P000 TDO TRST VDD1 5 * P002 P004 P007 P009 VSS 6 P008 P010 P011 P013 P015 7 P006 P016 P017 P019 VDD1 8 P005 P014 P021 P023 P025 9 P012 P018 P020 P027 VDD1 10 P003 P022 P024 P029 VSS P026 P028 P030 P031 VSS
7 P225 P227 P229 P234 P232 8 VSS
P221 P223 P224 P228
9 VDD3 P217 P219 P220 P230 10 P211 P213 P215 P218 P226 11 VSS 12 VSS
P209 VDD3 P216 P222 P207 VDD P212 P214
11 12
13 VDD3 P205 P206 P208 P210 14 VDD3 P203 P200 P204 P202 15 P199 P201 VDD3 P196 P198 16 VSS 17 VSS
P197 P194 P192 P190 P195 P188 P186 P184
P032 P034 VDD1 VDD1 P033 13 P001 P038 P036 P035 VDD1 14 P044 P042 P040 VDD1 P037 15 P050 P048 P046 P039 VSS P056 P054 P052 P041 VSS
16 17
18 VDD3 P193 P182 P180 P178 19 P191 P189 P187 P176 P174 20 VDD3 P185 P183 P172 P170 21 P181 P179 P177 P168 P164 22 VSS
P175 P173 P166 P160
P062 P058 P047 P045 P043 18 P064 P060 P051 P049 VDD 19 P068 P066 P055 P053 VSS
20
P072 P070 P061 P059 P057 21 P074 GT0 P065 P063 VSS
22
23 VDD3 P171 P167 P162 P158 P156 P150 P146 P148 P142 P152 P132 P126 P118 P112 P108 P100 P094 P090 P086 P082 VDD2 P078 VSS P071 P067 VDD1 23 24 P169 P165 P161 VSS VSS 25 26 27
P154 P144 VDD2 P140 P138 P136 P130 P124 P120 P114 P110 P102 P096 P092 P088 P084 P080 GT1 VSS P076 P073 P069 24
P163 P157 P159 P153 P149 P145 P139 P135 P131 P134 P128 P122 P116 VDD2 P106 P104 P098 P103 P099 P093 P089 VSS P155 VSS P147 P143 P137 P133 P129 P125 P123 P119 VDD2 P117 P113 P111 P109 P105 P101 P095 P091 VDD2 P127 VSS VSS P121 VDD2 P115 VSS VSS VDD2 P107 VDD P097 VSS
P083 P077 P075 VSS P087 P081 P079 VDD2 P085
25 26 27
P151 VDD2 VSS P141 VSS
AF AE AD AC AB AA
Y
X
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
Figure 30. IQX320 [PBGA/416L] Package Footprint
Notes:
(1) (2) (3) (4) (5) VDD1 - VDD.PAD1 VDD2 - VDD.PAD2 VDD3 - VDD.PAD3 VDD4 - VDD.PAD4 Pxxx/ - Port is dual function
June 2000
Revision 5.0
45
IQX Family Data Sheet
6.4 IQX240B [PQFP/304L] Package Pinout by Name
Name GC0 GC1 GC2 GC3 GT0 GT1 GT2 GT3 GT4 P000 P001 P002 P003 P004 P005 P006 P007 P008 P009 P010 P011 P012 P013 P014 P015 P016 P017 P018 P019 P020 P021 P022 P023 P024 P025 P026 P027 P028 Pin# 12 9 7 3 229 228 77 76 5 303 300 295 293 292 291 290 288 287 286 285 284 283 282 281 280 277 276 275 274 273 272 271 270 269 268 265 264 263 Name P029 P030 P031 P032 P033 P034 P035 P036 P037 P038 P039 P040 P041 P042 P043 P044 P045 P046 P047 P048 P049 P050 P051 P052 P053 P054 P055 P056 P057 P058 P059 P060 P061 P062 P063 P064 P065 P066 Pin# 262 261 260 259 258 257 256 255 254 251 250 249 248 247 246 245 244 243 240 239 238 237 236 234 233 232 231 230 227 226 225 224 223 220 219 218 217 216 Name P067 P068 P069 P070 P071 P072 P073 P074 P075 P076 P077 P078 P079 P080 P081 P082 P083 P084 P085 P086 P087 P088 P089 P090 P091 P092 P093 P094 P095 P096 P097 P098 P099 P100 P101 P102 P103 P104 Pin# 215 214 213 212 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 191 190 189 188 187 186 185 184 183 182 181 180 177 176 175 174 173 172 Name P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 Pin# 171 170 169 168 167 164 163 162 161 160 157 156 155 154 153 152 151 150 149 148 145 144 143 142 141 140 139 138 137 136 135 134 133 132 129 128 127 126 Name P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P158 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 P178 P179 P180 Pin# 125 124 123 122 121 120 117 116 115 114 111 110 109 108 107 106 105 104 Name P181 P182 P183 P184 P185 P186 P187 P188 P189 P190 P191 P192 P193 P194/GT12 P195/GT11 P196/GT10 P197/GT9 P198/GT8 Pin# 78 75 74 73 72 70 69 68 67 66 65 64 63 62 59 58 57 55 54 53 52 51 50 47 46 45 44 43 42 41 40 39 38 37 34 33 32 31 Name P219/CA3 P220/CA4 P221/CA5 P222/CA6 P223/CA7 P224/CA8 P225 P226/RA0 P227/RA1 P228/RA2 P229/RA3 P230/RA4 P231/RA5 P232/RA6 P233/RA7 P234/RA8 P235/P/S P236/C0 P237/C1 P238/WE P239/STROBE RCE TCK TDI TDO TMS TRST* VDD VDD VDD VDD VDD.PAD1 VDD.PAD1 VDD.PAD1 VDD.PAD1 VDD.PAD1 VDD.PAD2 VDD.PAD2 Pin# 30 29 27 26 25 24 23 22 19 18 17 16 15 14 13 11 8 6 4 2 1 304 298 302 299 301 294 56 113 210 242 235 253 267 279 297 158 165 Name VDD.PAD2 VDD.PAD2 VDD.PAD2 VDD.PAD3 VDD.PAD3 VDD.PAD3 VDD.PAD3 VDD.PAD3 VDD.PAD4 VDD.PAD4 VDD.PAD4 VDD.PAD4 VDD.X VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin# 178 192 221 84 147 101 119 131 20 35 48 60 28 10 21 36 49 61 71 83 90 100 112 118 130 146 159 166 179 193 211 222 241 252 266 278 289 296
103 P199/GC12 102 P200/GC11 99 98 97 96 95 94 93 92 91 89 88 87 86 85 82 81 80 79 P201/GC10 P202/GC9 P203/GC8 P204/K4 P205/K3 P206/K2 P207/K1 P208/K0 P209/GC7 P210/GC6 P211/GC5 P212/GC4 P213/GT7 P214/GT6 P215/GT5 P216/CA0 P217/CA1 P218/CA2
Table 23. IQX240B [PQFP/304L] Package Pinout by Name
46
Revision 5.0
June 2000
IQX Family Data Sheet
6.5 IQX240B [PQFP/304L] Package Pinout by Location
Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Name P239/STROBE P238/WE GC3 P237/C1 GT4 P236/C0 GC2 P235/P/S GC1 VSS P234/RA8 GC0 P233/RA7 P232/RA6 P231/RA5 P230/RA4 P229/RA3 P228/RA2 P227/RA1 VDD.PAD4 VSS P226/RA0 P225 P224/CA8 P223/CA7 P222/CA6 P221/CA5 VDD.X P220/CA4 P219/CA3 P218/CA2 P217/CA1 P216/CA0 P215/GT5 VDD.PAD4 VSS P214/GT6 P213/GT7 Pin# 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 Name P212/GC4 P211/GC5 P210/GC6 P209/GC7 P208/K0 P207/K1 P206/K2 P205/K3 P204/K4 VDD.PAD4 VSS P203/GC8 P202/GC9 P201/GC10 P200/GC11 P199/GC12 P198/GT8 VDD P197/GT9 P196/GT10 P195/GT11 VDD.PAD4 VSS P194/GT12 P193 P192 P191 P190 P189 P188 P187 P186 VSS P185 P184 P183 P182 GT3 Pin# 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 Name GT2 P181 P180 P179 P178 P177 VSS VDD.PAD3 P176 P175 P174 P173 P172 VSS P171 P170 P169 P168 P167 P166 P165 P164 P163 VSS VDD.PAD3 P162 P161 P160 P159 P158 P157 P156 P155 P154 P153 VSS VDD P152 Pin# 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 Name P151 P150 P149 VSS VDD.PAD3 P148 P147 P146 P145 P144 P143 P142 P141 P140 P139 VSS VDD.PAD3 P138 P137 P136 P135 P134 P133 P132 P131 P130 P129 P128 P127 P126 P125 VSS VDD.PAD3 P124 P123 P122 P121 P120 Pin# 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 Name P119 P118 P117 P116 P115 VDD.PAD2 VSS P114 P113 P112 P111 P110 VDD.PAD2 VSS P109 P108 P107 P106 P105 P104 P103 P102 P101 P100 P099 VDD.PAD2 VSS P098 P097 P096 P095 P094 P093 P092 P091 P090 P089 P088 Pin# 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 Name P087 VDD.PAD2 VSS P086 P085 P084 P083 P082 P081 P080 P079 P078 P077 P076 P075 P074 P073 P072 P071 VDD VSS P070 P069 P068 P067 P066 P065 P064 P063 P062 VDD.PAD2 VSS P061 P060 P059 P058 P057 GT1 Pin# 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 Name GT0 P056 P055 P054 P053 P052 VDD.PAD1 P051 P050 P049 P048 P047 VSS VDD P046 P045 P044 P043 P042 P041 P040 P039 P038 VSS VDD.PAD1 P037 P036 P035 P034 P033 P032 P031 P030 P029 P028 P027 P026 VSS Pin# 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 Name VDD.PAD1 P025 P024 P023 P022 P021 P020 P019 P018 P017 P016 VSS VDD.PAD1 P015 P014 P013 P012 P011 P010 P009 P008 P007 VSS P006 P005 P004 P003 TRST* P002 VSS VDD.PAD1 TCK TDO P001 TMS TDI P000 RCE
Table 24. IQX240B [PQFP/304L] Package Pinout by Location
June 2000
Revision 5.0
47
IQX Family Data Sheet
6.6 IQX240B [PQFP/304L] Package Pinout
304 303 302 301 300 299 298 297 296 295 294 293 292 291 290 289 288 287 286 285 284 283 282 281 280 279 278 277 276 275 274 273 272 271 270 269 268 267 266 265 264 263 262 261 260 259 258 257 256 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 240 239 238 237 236 235 234 233 232 231 230 229
RCE P000 TDI TMS P001 TDO TCK VDD.PAD1 VSS P002 TRST* P003 P004 P005 P006 VSS P007 P008 P009 P010 P011 P012 P013 P014 P015 VDD.PAD1 VSS P016 P017 P018 P019 P020 P021 P022 P023 P024 P025 VDD.PAD1 VSS P026 P027 P028 P029 P030 P031 P032 P033 P034 P035 P036 P037 VDD.PAD1 VSS P038 P039 P040 P041 P042 P043 P044 P045 P046 VDD VSS P047 P048 P049 P050 P051 VDD.PAD1 P052 P053 P054 P055 P056 GT0
48
VDD.PAD3 P176 P175 P174 P173 P172 VSS P171 P170 P169 P168 P167 P166 P165 P164 P163 VSS VDD.PAD3 P162 P161 P160 P159 P158 P157 P156 P155 P154 P153 VSS VDD P152 P151 P150 P149 VSS VDD.PAD3 P148 P147 P146 P145 P144 P143 P142 P141 P140 P139 VSS VDD.PAD3 P138 P137 P136 P135 P134 P133 P132 P131 P130 P129 P128 P127 P126 P125 VSS VDD.PAD3 P124 P123 P122 P121 P120
GT2 P181 P180 P179 P178 P177 VSS
77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152
239/STROBE P238/WE GC3 P237/C1 GT4 P236/C0 GC2 P235/ P/S GC1 VSS P234/RA8 GC0 P233/RA7 P232/RA6 P231/RA5 P230/RA4 P229/RA3 P228/RA2 P227/RA1 VDD.PAD4 VSS P226/RA0 P225 P224/CA8 P223/CA7 P222/CA6 P221/CA5 VDD.X P220/CA4 P219/CA3 P218/CA2 P217/CA1 P216/CA0 P215/GT5 VDD.PAD4 VSS P214/GT6 P213/GT7 P212/GC4 P211/GC5 P210/GC6 P209/GC7 P208/K0 P207/K1 P206/K2 P205/K3 P204/K4 VDD.PAD4 VSS P203/GC8 P202/GC9 P201/GC10 P200/GC11 P199/GC12 P198/GT8 VDD P197/GT9 P196/GT10 P195/GT11 VDD.PAD4 VSS P194/GT12 P193 P192 P191 P190 P189 P188 P187 P186 VSS P185 P184 P183 P182 GT3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76
I/O Ports Powered by VDD.PAD1
Top View
I/O Ports Powered by VDD.PAD3
228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153
GT1 P057 P058 P059 P060 P061 VSS VDD.PAD2 P062 P063 P064 P065 P066 P067 P068 P069 P070 VSS VDD P071 P072 P073 P074 P075 P076 P077 P078 P079 P080 P081 P082 P083 P084 P085 P086 VSS VDD.PAD2 P087 P088 P089 P090 P091 P092 P093 P094 P095 P096 P097 P098 VSS VDD.PAD2 P099 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 VSS VDD.PAD2 P110 P111 P112 P113 P114 VSS VDD.PAD2 P115 P116 P117 P118 P119
I/O Ports Powered by VDD.PAD4
Figure 31. IQX240B [PQFP/304L] Package Pinout
Revision 5.0
I/O Ports Powered by VDD.PAD2
June 2000
IQX Family Data Sheet
6.7 IQX160 [PQFP/208L] Package Pinout by Name
Name GC0 GC1 GT0 GT1 GT2 GT3 P000 P001 P002 P003 P004 P005 P006 P007 P008 P009 P010 P011 P012 P013 P014 P015 P016 P017 P018 P019 P020 P021 P022 P023 P024 P025 P026 P027 P028 P029 P030 P031 P032 P033 P034 P035 P036 P037 P038 P039 P040 P041 P042 P043 P044 P045 Pin# 10 7 157 156 53 52 203 202 201 200 198 197 196 195 194 192 191 190 189 188 187 184 183 182 181 180 179 177 176 175 174 173 172 170 169 168 167 166 165 162 161 160 159 158 155 154 153 152 151 150 147 146 Name P046 P047 P048 P049 P050 P051 P052 P053 P054 P055 P056 P057 P058 P059 P060 P061 P062 P063 P064 P065 P066 P067 P068 P069 P070 P071 P072 P073 P074 P075 P076 P077 P078 P079 P080 P081 P082 P083 P084 P085 P086 P087 P088 P089 P090 P091 P092 P093 P094 P095 P096 P097 Pin# 145 144 143 142 140 139 138 137 136 135 132 131 130 129 128 127 125 124 123 122 121 120 117 116 115 114 113 112 110 109 108 107 106 105 104 103 102 101 100 99 96 95 94 93 92 91 89 88 87 86 85 84 Name P098 P099 P100 P101 P102 P103 P104/GT12 P105/GT11 P106/GT10 P107 P108/GT9 P109/GT8 P110/GC12 P111/GC11 P112/GC10 P113 P114/GC9 P115/GC8 P116/K4 P117/K3 P118 P119 P120/K2 P121/K1 P122/K0 P123 P124 P125/GC7 P126/GC6 P127/GC5 P128/GC4 P129 P130 P131/GT7 P132/GT6 P133/GT5 P134/GT4 P135 P136 P137/GC3 P138/GC2 P139/ P/S P140/CA0 P141/CA1 P142/CA2 P143/CA3 P144/CA4 P145/CA5 P146/CA6 P147/CA7 P148/RA0 P149/RA1 Pin# 82 81 80 78 77 76 74 73 72 71 70 69 67 66 65 64 63 62 59 58 57 56 55 54 51 50 49 48 47 44 43 42 41 40 39 37 36 35 34 33 32 30 28 27 26 25 24 22 21 20 19 17 Name P150/RA2 P151/RA3 P152/RA4 P153/RA5 P154/RA6 P155/RA7 P156/C0 P157/C1 P158/WE P159/STROBE RCE TCK TDI TDO TMS TRST* VDD VDD VDD.PAD1 VDD.PAD1 VDD.PAD1 VDD.PAD1 VDD.PAD2 VDD.PAD2 VDD.PAD2 VDD.PAD2 VDD.PAD2 VDD.X VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin# 16 15 14 13 12 11 5 4 3 2 6 206 1 207 208 204 29 133 119 164 186 205 8 45 61 79 98 148 9 18 23 31 38 46 60 68 75 83 90 97 111 118 126 134 141 149 163 171 178 185 193 199
Table 25. IQX160 [PQFP/208L] Package Pinout by Name
June 2000
Revision 5.0
49
IQX Family Data Sheet
6.8 IQX160 [PQFP/208L] Package Pinout by Location
Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Name TDI P159/STROBE P158/WE P157/C1 P156/C0 RCE GC1 VDD.PAD2 VSS GC0 P155/RA7 P154/RA6 P153/RA5 P152/RA4 P151/RA3 P150/RA2 P149/RA1 VSS P148/RA0 P147/CA7 P146/CA6 P145/CA5 VSS P144/CA4 P143/CA3 P142/CA2 P141/CA1 P140/CA0 VDD P139/ P/S VSS P138/GC2 P137/GC3 P136 P135 P134/GT4 P133/GT5 VSS P132/GT6 P131/GT7 P130 P129 P128/GC4 P127/GC5 VDD.PAD2 VSS P126/GC6 P125/GC7 P124 P123 P122/K0 GT3 Pin# 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 Name GT2 P121/K1 P120/K2 P119 P118 P117/K3 P116/K4 VSS VDD.PAD2 P115/GC8 P114/GC9 P113 P112/GC10 P111/GC11 P110/GC12 VSS P109/GT8 P108/GT9 P107 P106/GT10 P105/GT11 P104/GT12 VSS P103 P102 P101 VDD.PAD2 P100 P099 P098 VSS P097 P096 P095 P094 P093 P092 VSS P091 P090 P089 P088 P087 P086 VSS VDD.PAD2 P085 P084 P083 P082 P081 P080 Pin# 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 Name P079 P078 P077 P076 P075 P074 VSS P073 P072 P071 P070 P069 P068 VSS VDD.PAD1 P067 P066 P065 P064 P063 P062 VSS P061 P060 P059 P058 P057 P056 VDD VSS P055 P054 P053 P052 P051 P050 VSS P049 P048 P047 P046 P045 P044 VDD.X VSS P043 P042 P041 P040 P039 P038 GT1 Pin# 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Name GT0 P037 P036 P035 P034 P033 VSS VDD.PAD1 P032 P031 P030 P029 P028 P027 VSS P026 P025 P024 P023 P022 P021 VSS P020 P019 P018 P017 P016 P015 VSS VDD.PAD1 P014 P013 P012 P011 P010 P009 VSS P008 P007 P006 P005 P004 VSS P003 P002 P001 P000 TRST* VDD.PAD1 TCK TDO TMS
Table 26. IQX160 [PQFP/208L] Package Pinout by Location
50
Revision 5.0
June 2000
IQX Family Data Sheet
6.9 IQX160 [PQFP/208L] Package Pinout
208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157
TMS TDO TCK VDD.PAD1 TRST* P000 P001 P002 P003 VSS P004 P005 P006 P007 P008 VSS P009 P010 P011 P012 P013 P014 VDD.PAD1 VSS P015 P016 P017 P018 P019 P020 VSS P021 P022 P023 P024 P025 P026 VSS P027 P028 P029 P030 P031 P032 VDD.PAD1 VSS P033 P034 P035 P036 P037 GT0
June 2000
GT2 P121/K1 P120/K2 P119 P118 P117/K3 P116/K4 VSS VDD.PAD2 P115/GC8 P114/GC9 P113 P112/GC10 P111/GC11 P110/GC12 VSS P109/GT8 P108/GT9 P107 P106/GT10 P105/GT11 P104/GT12 VSS P103 P102 P101 VDD.PAD2 P100 P099 P098 VSS P097 P096 P095 P094 P093 P092 VSS P091 P090 P089 P088 P087 P086 VSS VDD.PAD2 P085 P084 P083 P082 P081 P080
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
TDI P159/STROBE P158/WE P157/C1 P156/C0 RCE GC1 VDD.PAD2 VSS GC0 P155/RA7 P154/RA6 P153/RA5 P152/RA4 P151/RA3 P150/RA2 P149/RA1 VSS P148/RA0 P147/CA7 P146/CA6 P145/CA5 VSS P144/CA4 P143/CA3 P142/CA2 P141/CA1 P140/CA0 VDD P139/ P/S VSS P138/GC2 P137/GC3 P136 P135 P134/GT4 P133/GT5 VSS P132/GT6 P131/GT7 P130 P129 P128/GC4 P127/GC5 VDD.PAD2 VSS P126/GC6 P125/GC7 P124 P123 P122/K0 GT3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
I/O Ports Powered by VDD.PAD2
Top View
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
GT1 P038 P039 P040 P041 P042 P043 VSS VDD.X P044 P045 P046 P047 P048 P049 VSS P050 P051 P052 P053 P054 P055 VSS VDD P056 P057 P058 P059 P060 P061 VSS P062 P063 P064 P065 P066 P067 VDD.PAD1 VSS P068 P069 P070 P071 P072 P073 VSS P074 P075 P076 P077 P078 P079
Figure 32. IQX160 [PQFP/208L] Package Pinout
Revision 5.0
I/O Ports Powered by VDD.PAD1
51
IQX Family Data Sheet
6.10 IQX128B [PQFP/184L] Package Pinout by Name
Name GC0 GC1 GT0 GT1 GT2 GT3 P000 P001 P002 P003 P004 P005 P006 P007 P008 P009 P010 P011 P012 P013 P014 P015 P016 P017 P018 P019 P020 P021 P022 P023 P024 P025 P026 P027 P028 P029 P030 P031 P032 P033 P034 P035 P036 P037 P038 P039 Pin# 10 7 139 138 48 45 178 177 176 175 173 172 171 170 169 166 165 164 163 161 160 159 158 155 154 153 152 150 149 148 147 144 143 142 141 140 136 135 134 133 130 129 128 127 126 124 Name P040 P041 P042 P043 P044 P045 P046 P047 P048 P049 P050 P051 P052 P053 P054 P055 P056 P057 P058 P059 P060 P061 P062 P063 P064 P065 P066 P067 P068 P069 P070 P071 P072 P073 P074 P075 P076 P077 P078 P079 P080 P081 P082 P083 P084/GT12 P085/GT11 Pin# 123 122 121 120 117 116 115 114 113 111 110 109 108 107 104 103 102 101 100 98 97 96 95 94 92 90 89 88 87 84 83 82 81 80 78 77 76 75 74 71 70 69 68 67 65 64 Name P086/GT10 P087/GT9 P088/GT8 P089/GC12 P090/GC11 P091/GC10 P092/GC9 P093/GC8 P094/K4 P095/K3 P096/K2 P097/K1 P098/K0 P099/GC7 P100/GC6 P101/GC5 P102/GC4 P103/GT7 P104/GT6 P105/GT5 P106/GT4 P107/GC3 P108/GC2 P109/P/S P110/CA0 P111/CA1 P112/CA2 P113/CA3 P114/CA4 P115/CA5 P116/CA6 P117/RA0 P118/RA1 P119/RA2 P120/RA3 P121/RA4 P122/RA5 P123/RA6 P124/C0 P125/C1 P126/WE P127/STROBE RCE TCK TDI TDO Pin# 63 62 61 58 57 56 55 54 52 51 50 49 44 43 42 39 38 37 36 34 33 32 31 29 27 26 25 24 23 21 20 19 16 15 14 13 12 11 5 4 3 2 6 181 1 183 Name TMS TRST* VDD VDD VDD.PAD1 VDD.PAD1 VDD.PAD1 VDD.PAD1 VDD.PAD1 VDD.PAD1 VDD.PAD1 VDD.PAD2 VDD.PAD2 VDD.PAD2 VDD.PAD2 VDD.PAD2 VDD.PAD2 VDD.PAD2 VDD.X VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin# 184 179 28 118 146 93 106 137 157 168 180 47 8 18 40 60 73 86 131 41 9 17 22 30 35 46 53 59 66 72 79 85 91 99 105 112 119 125 132 145 151 156 162 167 174 182
Table 27. IQX128B [PQFP/184L] Package Pinout by Name
52
Revision 5.0
June 2000
IQX Family Data Sheet
6.11 IQX128B [PQFP/184L] Package Pinout by Location
Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Name TDI P127/STROBE P126/WE P125/C1 P124/C0 RCE GC1 VDD.PAD2 VSS GC0 P123/RA6 P122/RA5 P121/RA4 P120/RA3 P119/RA2 P118/RA1 VSS VDD.PAD2 P117/RA0 P116/CA6 P115/CA5 VSS P114/CA4 P113/CA3 P112/CA2 P111/CA1 P110/CA0 VDD P109/P/S VSS P108/GC2 P107/GC3 P106/GT4 P105/GT5 VSS P104/GT6 P103/GT7 P102/GC4 P101/GC5 VDD.PAD2 VSS P100/GC6 P099/GC7 P098/K0 GT3 VSS Pin# 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Name VDD.PAD2 GT2 P097/K1 P096/K2 P095/K3 P094/K4 VSS P093/GC8 P092/GC9 P091/GC10 P090/GC11 P089/GC12 VSS VDD.PAD2 P088/GT8 P087/GT9 P086/GT10 P085/GT11 P084/GT12 VSS P083 P082 P081 P080 P079 VSS VDD.PAD2 P078 P077 P076 P075 P074 VSS P073 P072 P071 P070 P069 VSS VDD.PAD2 P068 P067 P066 P065 VSS P064 Pin# 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 Name VDD.PAD1 P063 P062 P061 P060 P059 VSS P058 P057 P056 P055 P054 VSS VDD.PAD1 P053 P052 P051 P050 P049 VSS P048 P047 P046 P045 P044 VDD VSS P043 P042 P041 P040 P039 VSS P038 P037 P036 P035 P034 VDD.X VSS P033 P032 P031 P030 VDD.PAD1 GT1 Pin# 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Name GT0 P029 P028 P027 P026 P025 VSS VDD.PAD1 P024 P023 P022 P021 VSS P020 P019 P018 P017 VSS VDD.PAD1 P016 P015 P014 P013 VSS P012 P011 P010 P009 VSS VDD.PAD1 P008 P007 P006 P005 P004 VSS P003 P002 P001 P000 TRST* VDD.PAD1 TCK VSS TDO TMS
Table 28. IQX128B [PQFP/184L] Package Pinout by Location
June 2000
Revision 5.0
53
IQX Family Data Sheet
6.12 IQX128B [PQFP/184L] Package Pinout
184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139
TMS TDO VSS TCK VDD.PAD1 TRST* P000 P001 P002 P003 VSS P004 P005 P006 P007 P008 VDD.PAD1 VSS P009 P010 P011 P012 VSS P013 P014 P015 P016 VDD.PAD1 VSS P017 P018 P019 P020 VSS P021 P022 P023 P024 VDD.PAD1 VSS P025 P026 P027 P028 P029 GT0
TDI P127/STROBE P126/WE P125/C1 P124/C0 RCE GC1 VDD.PAD2 VSS GC0 P123/RA6 P122/RA5 P121/RA4 P120/RA3 P119/RA2 P118/RA1 VSS VDD.PAD2 P117/RA0 P116/CA6 P115/CA5 VSS P114/CA4 P113/CA3 P112/CA2 P111/CA1 P110/CA0 VDD P109/ P/S VSS P108/GC2 P107/GC3 P106/GT4 P105/GT5 VSS P104/GT6 P103/GT7 P102/GC4 P101/GC5 VDD.PAD2 VSS P100/GC6 P099/GC7 P098/K0 GT3 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
Top View
138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93
GT1 VDD.PAD1 P030 P031 P032 P033 VSS VDD.X P034 P035 P036 P037 P038 VSS P039 P040 P041 P042 P043 VSS VDD P044 P045 P046 P047 P048 VSS P049 P050 P051 P052 P053 VDD.PAD1 VSS P054 P055 P056 P057 P058 VSS P059 P060 P061 P062 P063 VDD.PAD1
54
VDD.PAD2 GT2 P097/K1 P096/K2 P095/K3 P094/K4 VSS P093/GC8 P092/GC9 P091/GC10 P090/GC11 P089/GC12 VSS VDD.PAD2 P088/GT8 P087/GT9 P086/GT10 P085/GT11 P084/GT12 VSS P083 P082 P081 P080 P079 VSS VDD.PAD2 P078 P077 P076 P075 P074 VSS P073 P072 P071 P070 P069 VSS VDD.PAD2 P068 P067 P066 P065 VSS P064
47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92
I/O Ports Powered by VDD.PAD2
Figure 33. IQX128B [PQFP/184L] Package Pinout
Revision 5.0
I/O Ports Powered by VDD.PAD1
June 2000
IQX Family Data Sheet 7.0 MECHANICAL SPECIFICATION
7.1 IQX320 [PBGA/416L] Package Dimensions
Top View
AF AE AD AC AB AA Y X W V U T R P N M L K J H G F E D C B A
IQX320 PB416 F5N42A USA
Pin A1 Marking 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0.50 (0.0197)
1.50 0.2 (0.059 .0079)
0.60 (0.0236)
Cross-sectional View
20.24 (0.797)
AF AE AD AC AB AA Y X W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
1.27 mm. (0.050) (in.)
35 (1.378)
Bottom View (Ball Side)
Figure 34. IQX320 [PBGA/416L] Package Dimensions
Note:
(1) Use "mm" as the controlling dimension. June 2000 Revision 5.0 55
IQX Family Data Sheet
7.2 PQFP Package Dimensions
E E1
D1 D
Top View
W 8 - 12 A2
Side View
X
0 - 7
A1
A
Dimension in mm. (in.) 0.10 (0.004)
L
e Detail W
B Detail X
Figure 35. PQFP Package Dimensions
Note:
(1) Use "mm" as the controlling dimension
Package Dimension Table A max A1 min max A2 min max D min max D1 min max E min max E1 min max L min max B min max e BSC. PQFP/304L inch mm 0.172 4.37 0.011 0.28 0.019 0.47 0.146 3.70 0.154 3.90 1.669 42.40 1.685 42.80 1.571 39.90 1.618 40.10 1.669 42.40 1.685 42.80 1.571 39.90 1.618 40.10 0.020 0.50 0.028 0.75 0.007 0.17 0.011 0.27 0.0197 0.50 PQFP/208L inch mm 0.157 3.99 0.010 0.25 0.017 0.43 0.135 3.43 0.140 3.56 1.195 30.40 1.215 30.91 1.098 27.93 1.106 28.14 1.195 30.40 1.215 30.91 1.098 27.93 1.106 28.14 0.018 0.46 0.030 0.76 0.006 0.15 0.011 0.28 0.0197 0.50 PQFP/184L inch mm 0.157 3.99 0.010 0.25 0.017 0.43 0.135 3.43 0.140 3.56 1.219 31.01 1.238 31.49 1.098 27.93 1.106 28.14 1.219 31.01 1.238 31.49 1.098 27.93 1.106 28.14 0.029 0.74 0.041 1.04 0.006 0.15 0.011 0.28 0.0197 0.50
Table 29. PQFP Package Dimensions
56
Revision 5.0
June 2000
IQX Family Data Sheet 8.0 PACKAGE THERMAL CHARACTERISTICS
Package PQFP Pin Count 184 208 304 PBGA 416 JC(C/W) 6.6 6.6 6.3 1.7 JA(C/W) Still Air 37.4 36.6 21.6 13.8 JA(C/W) 200 Ifpm 28.3 27.4 19.3 10.6 JA(C/W) 400 Ifpm 24.2 24.0 17.9 9.2 JA(C/W) 600 Ifpm 21.7 21.4 16.3 8.5
Table 30. Package Thermal Coefficients
Note:
(1) Thermal performance values are based on simulation data.
June 2000
Revision 5.0
57
IQX Family Data Sheet 9.0 TABLES FOR DETERMINING DIE PAD TO I/O PORT PIN MAPPING AND LOCATIONS OF REAL SRAM CELL
The following tables help determine the locations of the real SRAM cells in the Switch Matrix. The SRAM cell controlling the connection between I/O Port "i" and I/O Port "j" is determined as follows: Get the Index values corresponding to I/O Port numbers "i" and "j". If the index value for "i" is greater than index value for "j", then the SRAM cell has the row (word) address i* and column (bit) address j*, otherwise it has row address of j* and column address of i*. The numbers i* and j* represent the I/O Port locations on the die. Ex 1: On the IQX160, the SRAM cell controlling the connection between I/O Port 20 and I/O Port 100 is at location: Row addr = 20, Col Addr = 100; because the index for I/O Port 20 is 82, and it is greater than the index for I/O Port 100 which is 79. Ex 2: On the IQX240B, the SRAM cell controlling the connection between I/O Port 80 and I/O Port 180 is at location: Row addr = 241, Col Addr = 110; because the index value for I/O Port 80 is 120, and it is less than the index value for I/O Port 180 which is 313. Note that the IQX240B is a bondout version of IQX320 die, and the I/O Ports 80 and 180 on the device package are the I/O Ports 110 and 241 respectively.
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Revision 5.0
June 2000
IQX Family Data Sheet
Die PAD and IQX320 I/O Port 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
IQX240B I/O Port Index 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 2 6 10 14 18 22 26 30 34 38 42 46 50 54 58 62 66 70 74 78 82 86 90 94 98 102 106 110 114 118 122 126 130 134 138 142 146 150 154 158
Die PAD and IQX320 I/O Port 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79
IQX240B I/O Port Index 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 162 166 170 174 178 182 186 190 194 198 202 206 210 214 218 222 226 230 234 238 242 246 250 254 258 262 266 270 274 278 282 286 290 294 298 302 306 310 314 318
Die PAD and IQX320 I/O Port 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119
IQX240B I/O Port Index 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100 104 108 112 116 120 124 128 132 136 140 144 148 152 156
Die PAD and IQX320 I/O Port 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159
IQX240B I/O Port Index 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 160 164 168 172 176 180 184 188 192 196 200 204 208 212 216 220 224 228 232 236 240 244 248 252 256 260 264 268 272 276 280 284 288 292 296 300 304 308 312 316
Table 31. IQX320 and IQX240B I/O Port Pin Mapping
June 2000
Revision 5.0
59
IQX Family Data Sheet
Die PAD and IQX320 I/O Port 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 Die PAD and IQX320 I/O Port 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 Die PAD and IQX320 I/O Port 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 Die PAD and IQX320 I/O Port 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319
IQX240B I/O Port Index 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 319 315 311 307 303 299 295 291 287 283 279 275 271 267 263 259 255 251 247 243 239 235 231 227 223 219 215 211 207 203 199 195 191 187 183 179 175 171 167 163
IQX240B I/O Port Index 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 159 155 151 147 143 139 135 131 127 123 119 115 111 107 103 99 95 91 87 83 79 75 71 67 63 59 55 51 47 43 39 35 31 27 23 19 15 11 7 3
IQX240B I/O Port Index 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 317 313 309 305 301 297 293 289 285 281 277 273 269 265 261 257 253 249 245 241 237 233 229 225 221 217 213 209 205 201 197 193 189 185 181 177 173 169 165 161
IQX240B I/O Port Index 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 157 153 149 145 141 137 133 129 125 121 117 113 109 105 101 97 93 89 85 81 77 73 69 65 61 57 53 49 45 41 37 33 29 25 21 17 13 9 5 1
Table 31. IQX320 and IQX240B I/O Port Pin Mapping (Continued)
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Revision 5.0
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IQX Family Data Sheet
Die PAD and IQX160 I/O Port 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 Die PAD and IQX160 I/O Port 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 Die PAD and IQX160 I/O Port 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159
128B Port Index 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 2 6 10 14 18 22 26 30 34 38 42 46 50 54 58 62 66 70 74 78 82 86 90 94 98 102 106 110 114 118 122 126 130 134 138 142 146 150 154 158
IQX128B I/O Port Index 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100 104 108 112 116 120 124 128 132 136 140 144 148 152 156
IQX128B I/O Port Index 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 159 155 151 147 143 139 135 131 127 123 119 115 111 107 103 99 95 91 87 83 79 75 71 67 63 59 55 51 47 43 39 35 31 27 23 19 15 11 7 3
IQX128B I/O Port Index 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 157 153 149 145 141 137 133 129 125 121 117 113 109 105 101 97 93 89 85 81 77 73 69 65 61 57 53 49 45 41 37 33 29 25 21 17 13 9 5 1
Table 32. IQX160 and IQX128B I/O Port Pin Mapping
June 2000
Revision 5.0
61
IQX Family Data Sheet 10.0 COMPONENT AVAILABILITY AND ORDERING INFORMATION
The following table lists the IQX devices and the different package options, and speed grades available. Package Pins Type Code
IQX320 -12 -10 IQX240B -12 -10 IQX160 -10 -7 IQX128B -10 -7 X X X X X X
184 PQFP PQ184
208 PQFP PQ208
304 PQFP PQ304
416 PBGA PB416
X X
Table 33. Component Availability
Device
IQX320
Speed
-12 -10
Package*
PB 416 PB 416 PQ 304 PQ 304 PQ 208 PQ 208 PQ 184 PQ 184
Ordering#
IQX320-PB416 IQX320-10PB416 IQX240B-PQ304 IQX240B-10PQ304 IQX160-PQ208 IQX160-7PQ208 IQX128B-PQ184 IQX128B-7PQ184
IQX240B
-12 -10
IQX160
-10 -7
IQX128B
-10 -7
Table 34. Ordering Information
* PB=Plastic Ball Grid Array, PQ=Plastic Quad Flat Pack
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Revision 5.0
June 2000
IQX Family Data Sheet 11.0 IQX FAMILY AT A GLANCE
Feature Number of Usable I/O Port Pins Switch Matrix Size Programmable I/O Port Attributes Signal Direction Dataflow IN, OUT, BIDIR Flow-through, Latched, Clocked Clock, Clock Enable, Input Tristate, Output Tristate 4 9 5 8 23 / 22 7.5 ns 180 Mbs 133 MHz 12 mA 3V and/or 5V 0.6 391 PPGA 416 PBGA IN, OUT, BIDIR Flow-through, Latched, Clocked Clock, Clock Enable, Input Tristate, Output Tristate 4 9 5 8 23 / 22 7.5 ns 180 Mbs 133 MHz 12 mA 3V and/or 5V 0.6 304 PQFP 304 MQUAD IN, OUT, BIDIR Flow-through, Latched, Clocked Clock, Clock Enable, Input Tristate, Output Tristate 2 11 4 9 21/20 7.5 ns 200 Mbs 133 MHz 12 mA 3V and/or 5V 0.6 208 PQFP 208 MQUAD IN, OUT, BIDIR Flow-through, Latched, Clocked Clock, Clock Enable, Input Tristate, Output Tristate 2 11 4 9 19/18 7.5 ns 200 Mbs 133 MHz 12 mA 3V and/or 5V 0.6 184 PQFP 184 MQUAD 320 320 lines IQX320 IQX240B 240 240 lines 160 160 lines IQX160 IQX128B 128 128 lines
Control Signals
Number of Clock Control Pins dedicated shared with I/O Port Pins Number of Tristate Control Pins dedicated shared with I/O Port Pins I/O Ports Used By RapidConfigure Interface Pin-to-Pin Delay NRZ Data Rate Maximum Clock Frequency I/O Current Drive I/O Voltage Process Packages
Table 35. IQX Family at a Glance
63
Revision 5.0
June 2000
IQX Family Data Sheet 12.0 PRODUCT STATUS DEFINITIONS
Data Sheet Identification
Advanced
Product Status
Formative or In Design
Definition
This data sheet contains the design specifications for product development. Specification may change in any manner without notice. This data sheet contains the preliminary data, and supplementary data will be published at a later date. I-Cube reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. I-Cube reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains specifications for a product that has been discontinued by I-Cube. The data sheet is provided for reference information only.
Preliminary
Preproduction Product
No Identification
Full Production
Obsolete
No longer in Production
I-Cube(R) is a registered trademark and RapidConnect, RapidConfigure, ActiveArray, ImpliedDisconnect, IQ, IQX, MSX, MSXPro, OCX and PSX are trademarks of I-Cube, Inc. All other trademarks or registered trademarks are the property of their respective holders. I-Cube, Inc., does not assume any liability arising out of the applications or use of the product described herein; nor does it convey any license under its patents, copyright rights or any rights of others. The information contained in this document is believed to be current and accurate as of the publication date. I-Cube reserves the right to make changes, at any time, in order to improve reliability, function, performance or design in order to supply the best product possible. I-Cube assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. LIFE SUPPORT APPLICATIONS I-Cube products are not designed for use in life support appliances, devices, or systems where malfunction of an I-Cube product can reasonably be expected to result in personal injury. I-Cube customers using or selling I-Cube products for use in such application do so at their own risk and agree to fully indemnify I-Cube for any damages resulting from such improper use or sale. This product is protected under the U.S. patents: 5202593, 5282271, 5426738, 5428750, 5428800, 5465056, 5530814, 5559971, 5625780, 5710550, 5717871, 5734334, 5754791, 5781717, 5790048. Additional patents pending. IQX Family Data Sheet--Revision 5.0, June 2000 Previously printed as IQX Family Data Sheet--Revision 4.0, February 2000 Copyright (c) 1992-2000 I-Cube, Inc. All rights reserved. Unpublished--rights reserved under the copyright laws of the United States. Use of copyright notices is precautionary and does not imply publication or disclosure.
I-Cube(R), Inc.
2605 S. Winchester Blvd. Campbell, CA 95008, USA Phone: Fax: Email: Internet: +(408) 341-1888 +(408) 341-1899 marketing@icube.com http://www.icube.com IQX Family Data Sheet Revision 5.0, June 2000 Document # MKT-IQXFamily-DS
64
Revision 5.0
June 2000
IQX Family Data Sheet
65
Revision 5.0
June 2000

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